74GTL1655A

74GTL1655A STMICROELECTRONICS | Alldatasheet

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I HIGH SPEED GTL/GTL+ UNIVERSAL TRANSCEIVER: t PD = 4.6 ns (MAX.) A to B at VCC = 3V I COMBINES D-TYPE LATCHES AND D-TYPE FLIP-FLOPS FOR OPERATION IN TRANSPARENT, LATCHED, OR CLOCKED MODE I OPERATING VOLTAGE RANGE: V CC (OPR) = 3.0V to 3.6V I SYMMETRICAL OUTPUT IMPEDANCE: OH | = IOL =24mA (MIN) at VCC = 3V (A PORT) I OUTPUT IMPEDANCE: I OL = 100mA (MIN) at VCC = 3V (B PORT) I HIGH-IMPEDANCE STATE DURING POWER UP AND POWER DOWN up to V CC =BIASV CC =1.5V PERMITT LIVE INSERTION I B-PORT PRECHARGED BY BIASV CC REDUCE NOISE ON THE LINE DURING LIVE INSERTION I EDGE RATE-CONTROL INPUT CONFIGURES THE B-PORT OUTPUT RISE AND FALL TIMES I BUS HOLD ON DATA INPUTS ELIMINATES THE NEED FOR EXTERNAL PULL-UP/ PULL-DOWN RESISTORS (A PORT) I DISTRIBUTED V CC AND GND PIN CONFIGURATION MINIMIZES HIGH-SPEED SWITCHING NOISE IN PARALLEL COMUNICATIONS I PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 1655

DESCRIPTION

The 74GTL1655A devices are 16-bit high-drive (100mA), low-output-impedance universal bus transceivers designed for backplane applications. The 74GTL1655A devices provide live-insertion capability for backplane applications by tolerating active signals on the data ports when the devices are powered off. In addition, a biasing pin preconditions the GTL/GTL+ port to minimize disruption to an active backplane. The edge rate-control (V ERC ) input is provided so the rise and fall time of the B outputs can be configured to optimize for various backplane loading conditions. Data flow in each direction is 74GTL1655A

16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS

TRANSCEIVERS WITH LIVE INSERTION Table 1: Order Codes PACKAGE T & R TSSOP 74GTL1655ATTR TSSOP Figure 1: Pin Connection Rev. 1 Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s) 74GTL1655A controlled by output-enable (OEAB and OEBA ), latch-enable (LEAB and LEBA), and clock (CLK) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLK is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLK. The output enable (OE) is used to disable both ports simultaneously. Active bus-hold circuitry is provided on the A port to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5V, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. All input and output are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description PIN N° SYMBOL NAME AND FUNCTION 1, 2 1OEAB , 1OEBA Output Enable Input 4, 6, 7, 9, 11, 13, 14, 16 1A1 to 1A8 Data Inputs/Outputs LVTTL 17, 19, 20, 22, 23, 25, 27, 29 2A1 to 2A8 Data Inputs/Outputs LVTTL 31, 32 2OEAB , 2OEBA Output Enable Input

33 OE Output Enable Input

34, 35 2LEBA, 2LEAB Latch Enable

36 BIAS V CC Pre-Charge Supply Voltage

37, 38, 40, 42, 43, 45, 46, 48 2B8 to 2B1 Data Inputs/Outputs GTL/GTL+

41 V REF GTL Voltage Reference Input

49, 51, 52, 54, 55, 56, 58, 59 2A1 to 2A8 Data Inputs/Outputs GTL/GTL+

61 V ERC Edge Rate Control

62, 63 1LEBA, 1LEAB Latch Enable

64 CLK Clock Input (LOW to HIGH edge triggered)

39, 44, 47, 53, 57, 60 GND Ground (0V) 3, 15, 28, 50 V CC Positive Supply Voltage

Obsolete Product(s) - Obsolete Product(s) 74GTL1655A Table 3: Function Table (1) 1) A to B data flow is shown. B to A flow is similar, but uses OEBA, LEBA and CLK 2) Output level before the indicated steady-state input conditions were established, provided that CLK was high before LEAB went low 3) Output level before the indicated steady-state input conditions were established Table 4: Output Enable Truth Table Table 5: B-Port Edge Rate Control (VERC ) Truth Table INPUTS OUTPUT MODE OEAB LEAB CLK A B HXXXZ I s o l a t i o n L H X L L Transparent L H X H H Transparent LL LL R e g i s t e r e d L L H H Registered LLH X B0 (2) Previous State LLLX B0(3) Previous State INPUTS OUTPUTS OE OEAB OEBA A PORT B PORT L L L Active Active LLHZ A c t i v e LHL A c t i v e Z LHHZZ HXXZZ INPUT V ERC OUTPUT B PORT EDGE RATE LOGIC LEVEL NOMINAL VOLTAGE H VCC Slow LG N D F a s t

Obsolete Product(s) - Obsolete Product(s) 74GTL1655A Figure 3: Logic Diagram

Obsolete Product(s) - Obsolete Product(s) 74GTL1655A Table 6: Absolute Maximum Ratings Absolute Maximum Rating are those value beyond which damage to the device may occur. Functional operation under these condition is not implied Table 7: Recommended Operating Conditions 1) VTT and RTT can be adjusted to adapt backplane impedance if DC recommended IOL ratings are not exceeded 2) VREF can be adjusted to optimize noise margin (typ two-thirds VTT) Symbol Parameter Value Unit VCC Supply Voltage, Bias VCC -0.5 to +4.6 V VIA DC Input Voltage A Side, Control Input -0.5 to +4.6 V VIB DC Input Voltage B Side, VERC , VREF -0.5 to +4.6 V VOA DC Output Voltage A Side -0.5 to +4.6 V VOB DC Output Voltage B Side -0.5 to +4.6 V IIK DC Input Diode Current - 50 mA IOK DC Output Diode Current - 50 mA IOA DC Output Current A Side ± 48 mA IOB DC Output Current B Side in the Low State 200 mA Tstg Storage Temperature -65 to +150 °C TL Lead Temperature (10 sec) 300 °C Symbol Parameter Value Unit Min. Typ. Max. VCC Supply Voltage 3.0 3.3 3.6 V VI Input Voltage B port 0 VTT Vother 0 VCC VIH High Level Input Voltage B port V REF +0.05 V other 2 VIL Low Level Input Voltage B port V REF -0.05 V other 0.8 IIK Input Clamp Current -18 mA IOH High Level Output Current A port -24 mA IOL Low Level Output Current A port 24 mAB port 100 dt/dVCC Power -up ramp rate 200 µs/V Top Operating Temperature -40 85 °C

Obsolete Product(s) - Obsolete Product(s) 74GTL1655A Table 8: DC Specifications (*) For I/O ports, the parameter IOZ includes the input leakage current (**) Is also guaranteed when connecting BiasVCC with VCC . Symbol Parameter Test Condition Value UnitVCC (V) -40 to 85 °C Min. Typ. Max. VIK High Level Input Voltage 3- 1 . 2 V VOHA High Level Output Voltage A Port 3 to 3.6 IO =-100µAV CC -0.2 V3 IO =-12mA 2.4 3 IO =-24mA 2.2 VOLA Low Level Output Voltage A Port 3 to 3.6 IO =100µA 0.2 V3 IO =12mA 0.4 3 IO =24mA 0.55 VOLB Low Level Output Voltage B Port 3 IO =40mA 0.2 V3 IO =80mA 0.4 3 IO =100mA 0.5 II Input Current Control 3.6 VI = VCC or GND ±10 µA B Port 3.6 VI = VTT or GND ±10 µA Ioff Power Off Leakage Current 0V I or VO = 0 to 3.6V ±100 µA II(HOLD) Bus Hold A Port Input Current 3 VI = 0.8V 75 20 µA3 VI = 2V -75

3.6 VI = 0 to VCC ± 500

IOZHB 3-State Output Current B Port 3.6 V O = 1.5V 10 µA IOZLB 3-State Output Current B Port 3.6 V O = 0.4V -10 µA IOZ (*) 3-State Output Current A Port

3.6 V O = VCC or GND ±10 µA

IOZPU 3-State Output Current A Port 0 to 1.5 V O = 0.5 to 3V OE = LOW ±50 µA IOZPD 3-State Output Current A Port 1.5 to 0 V O = 0.5 to 3V OE = LOW ±50 µA ICC Quiescent Supply Current

3.6 V I = VCC or GND

IO =0 10 40 mA ∆ICC ∆ Supply Current except B port 3.6 VIN = VCC or GND One input VCC =0.6V 1m A C I Control Input Capaci- tance VIN = VCC or GND 35 p F C O Input Capacitance A Port VO = VCC or GND 56 pFInput Capacitance B Port 6 8

Obsolete Product(s) - Obsolete Product(s) 74GTL1655A Table 9: Live Insertion Specifications Table 10: AC Electrical Characteristics for GTL (VCC =3.3 ± 0.3V, VTT=1.2V, VREF =0.8V, VERC =V CC or GND) Symbol Parameter Test Condition Value UnitVCC (V) -40 to 85 °C Min. Typ. Max. ICC (Bias VCC ) Quiescent Bias Current 0 to 3.0 VO(Bport) = 0 to 1.2V 5 mA 3 to 3.6 VI(Bias Vcc) = 3 to 3.6V 10 µA VO Output Voltage B Port 0 V I(Bias Vcc) = 3.3V 1 1.2 V IO Output Current B Port 0 V O(Bport) = 0.4V VI(Bias Vcc) = 3 to 3.6V -1 µA 0 to 3.6 OE = 3.3V 100 µA 0 to 1.5 OE = 0 to 3.3V 100 µA Symbol Parameter Test Condition Value Unit-40 to 85 °C Min. Typ. Max. fMAX Maximum Frequency A to B or B to A

160 MHz

tPLH Propagation Delay Time A to B VERC =V CC R1=12.5Ω CL=30pF 1.5 5.2 nstPHL 1.5 6.2 tPLH Propagation Delay Time CK to B VERC =V CC RL=12.5Ω CL=30pF 1.5 5.5 nstPHL 1.5 5.8 tPLH Propagation Delay Time LEAB to B VERC =V CC RL=12.5Ω CL=30pF 1.5 5.8 nstPHL 1.5 6.4 tEN Enable Delay Time OEAB or OE to B VERC =V CC RL=12.5Ω CL=30pF 1.5 5.4 nstDIS Disable Delay Time OEAB or OE to B 1.5 6.2 tPLH Propagation Delay Time A to B VERC =GND R L=12.5Ω CL=30pF 1.5 4.3 nstPHL 1.5 4.6 tPLH Propagation Delay Time CK to B VERC =GND R L=12.5Ω CL=30pF 1.5 4.3 nstPHL 1.5 4.9 tPLH Propagation Delay Time LEAB to B VERC =GND R L=12.5Ω CL=30pF 1.5 4.9 nstPHL 1.5 4.8 tEN Enable Delay Time OEAB or OE to B VERC =GND R L=12.5Ω CL=30pF 1.5 4.8 nstDIS Disable Delay Time OEAB or OE to B 1.5 4.2 tPLH Propagation Delay Time B to A R L=500Ω C L=50pF 1.5 4.7 nstPHL 1.5 4.8 tPLH Propagation Delay Time CK to A R L=500Ω C L=50pF 1.5 4 nstPHL 1.5 4 tPLH Propagation Delay Time LEBA to A R L=500Ω C L=50pF 1.5 4 nstPHL 1.5 3.7

Obsolete Product(s) - Obsolete Product(s) 74GTL1655A Table 11: AC Electrical Characteristics for GTL+ (VCC =3.3 ± 0.3V, VTT=1.5V, VREF =1.0V, VERC =V CC or GND) tEN Enable Delay Time OEBA or OE to A R L=500Ω R1=500Ω C L=50pF 1 4.6 nstDIS Disable Delay Time OEBA or OE to A 16 . 1 tSU Set-up Time Data before clock 2.7 nsData before LE Ck High 2.8 Ck Low 2.6 tH Hold Time Data after clock 0.4 nsData after LE Ck High or LOW 0.9 tW Pulse duration LE High 3 nsCK High or Low 3 Slew rate Slew rate B output both transition (0.6 to 1.3V) VERC =V CC 1 ns/VVERC =GND 1 tsk Skew between drivers (in the same package) Switching in the same direction 1 nsSwitching in any direction 1 Symbol Parameter Test Condition Value Unit-40 to 85 °C Min. Typ. Max. fMAX Maximum Frequency B to A or A to B 160 MHz tPLH Propagation Delay Time A to B VERC =V CC RL=12.5Ω CL=30pF 1.5 5.1 nstPHL 1.5 6.5 tPLH Propagation Delay Time CK to B VERC =V CC RL=12.5Ω CL=30pF 1.5 5.4 nstPHL 1.5 6.2 tPLH Propagation Delay Time LEAB to B VERC =V CC RL=12.5Ω CL=30pF 1.5 5.7 nstPHL 1.5 6.7 tEN Enable Delay Time OEAB or OE to B VERC =V CC RL=12.5Ω CL=30pF 1.5 5.5 nstDIS Disable Delay Time OEAB or OE to B 1.5 5.8 tPLH Propagation Delay Time A to B VERC =GND R L=12.5Ω CL=30pF 1.0 4.3 nstPHL 1.0 4.9 tPLH Propagation Delay Time CK to B VERC =GND R L=12.5Ω CL=30pF 1.0 4.0 nstPHL 1.0 5.5 tPLH Propagation Delay Time LEAB to B VERC =GND R L=12.5Ω CL=30pF 1.0 4.0 nstPHL 1.0 5.4 tEN Enable Delay Time OEAB or OE to B VERC =GND R L=12.5Ω CL=30pF 1.0 5.1 nstDIS Disable Delay Time OEAB or OE to B 1.0 4.9 Symbol Parameter Test Condition Value Unit-40 to 85 °C Min. Typ. Max.

Obsolete Product(s) - Obsolete Product(s) 74GTL1655A Figure 4: Test Circuit For "A" Outputs C L = 50pF or equivalent (includes jig and probe capacitance) R L = R1 = 500Ω or equivalent R T = ZOUT of pulse generator (typically 50Ω ) tr=tf <=2.5ns tPLH Propagation Delay Time B to A R L=500Ω C L=50pF 1.5 4.8 nstPHL 1.5 4.7 tPLH Propagation Delay Time CK to A R L=500Ω C L=50pF 1.5 4.4 nstPHL 1.5 4.1 tPLH Propagation Delay Time LEBA to A R L=500Ω C L=50pF 1.5 4 nstPHL 1.5 3.7 tEN Enable Delay Time OEBA or OE to A R L=500Ω R1=500Ω C L=50pF 1 4.2 nstDIS Disable Delay Time OEBA or OE to A 16 . 1 Slew rate Slew rate B output both transition (0.6 to 1.3V) VERC =V CC RL=12.5Ω CL=30pF 1 ns/VVERC =GND R L=12.5Ω CL=30pF 1 tW Pulse duration LE High 3 nsCK High or Low 3 tSU Set-up Time Data before clock 2.7 nsData before LE Ck High 2.8 Ck Low 2.6 tH Hold Time Data after clock 0.4 nsData after LE Ck High or LOW 0.9 tsk Skew between drivers (in the same package) Switching in the same direction 1 nsSwitching in any direction 1 Test Switch tPLH, tPHL Open tPZL, tPLZ 6V tPZH, tPHZ GND Symbol Parameter Test Condition Value Unit-40 to 85 °C Min. Typ. Max.

Obsolete Product(s) - Obsolete Product(s) 74GTL1655A Figure 9: Waveform - Enable And Disable Time (A Port)

Obsolete Product(s) - Obsolete Product(s) 74GTL1655A DIM. mm. inch A 1.1 0.043 A1 0.05 0.15 0.002 0.006 A2 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 D 16.9 17.1 0.665 0.673 E 8.1 0.318 E1 6.0 6.2 0.236 0.244 e 0.5 BSC 0.0197 BSC K0 ˚ 8 ˚0 ˚ 8 ˚ L 0.50 0.75 0.020 0.030 TSSOP64 MECHANICAL DATA c Eb A2A D PIN 1 IDENTIFICATION A1 LKe 7187824A

Obsolete Product(s) - Obsolete Product(s) 74GTL1655A DIM. mm. inch A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362 T 30.4 1.197 Ao 8.7 8.9 0.342 0.350 Bo 17.2 17.4 0.677 0.685 Ko 1.4 1.6 0.055 0.063 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 Tape & Reel TSSOP64 MECHANICAL DATA

Obsolete Product(s) - Obsolete Product(s) 74GTL1655A Table 13: Revision History Date Revision Description of Changes 18-Oct-2004 1 First Release.

Obsolete Product(s) - Obsolete Product(s) 74GTL1655A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners © 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America