74FR74 FAIRCHILD | Alldatasheet

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■ 74FR74 is pin-for-pin compatible with the 74F74 ■ True 150 MHz fMAX capability on 74FR74 ■ Outputs sink 24 mA and source 24 mA ■ Guaranteed pin-to-pin skew specifications Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 74FR74 74FR1074 Order Number Package Number Package Description 74FR74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74FR74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74FR1074SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74FR1074PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2 74FR74 • 74FR1074 Logic Symbols 74FR74 74FR1074 Pin Descriptions Truth Tables 74FR74 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial /c17 = Rising Edge Q 0 = Previous Q(Q) before LOW-to-HIGH Clock Transition 74FR1074 H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial /c16 = Falling Edge Q 0 = Previous Q(Q) before HIGH-to-LOW Clock Transition Pin Names Description D n Data Inputs CP n Clock Inputs SDn Asynchronous Set Inputs C Dn Asynchronous Clear Inputs Q n True Output Q n Complementary Output Inputs Outputs SD CD CP D Q Q LHX X HL HLX X LH LLX X H H HH /c17 HH L HH /c17 LL H HHL X Q 0 Q 0 Inputs Outputs SD CD CP DQ Q LHX X HL HLX X LH LLX X H H HH /c16 HH L HH /c16 LL H HHL X Q 0 Q 0

3 www.fairchildsemi.com 74FR74 • 74FR1074 Logic Diagrams 74FR74 74FR1074 Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

www.fairchildsemi.com 4 74FR74 • 74FR1074 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 2000V Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized HIGH Signal VIL Input LOW Voltage 0.8 V Recognized LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 2.5 V Min I OH = −1 mA Voltage 2.4 V Min I OH = −3 mA

2.0 V Min I OH = −24 mA

VOL Output LOW Voltage 0.5 V Min I OL = 24 mA IIH Input HIGH Current 5 µAM a x V IN = 2.7V IBVI Input HIGH Current 7 µAM a x V IN = 7.0V Breakdown Test IIL Input LOW Current −150 µAM a x V IN = 0.5V (Dn, CPn) −1.8 mA Max V IN = 0.5V (CDn , SDn ) VID Input Leakage Test 4.75 V 0.0 I ID = 1.9 µA, All Other Pins Grounded IOD Output Circuit 3.75 V 0.0 V IOD = 150 mV, Leakage Test All Other Pins Grounded IOS Output Short-Circuit Current −100 −275 mA Max V OUT = 0.0V ICEX Output HIGH 50 µAM a x V OUT = VCC Leakage Current ICC Power Supply Current 24 mA Max

5 www.fairchildsemi.com 74FR74 • 74FR1074 Note 3: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL ) or LOW-to-HIGH (tOSLH ) or in opposite directions both HL and LH (tOST ). tOST is guaranteed by design. AC Operating Requirements 74FR74 Note 4: This specification is guaranteed by design. Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max fMAX Maximum Clock Frequency 150 190 150 MHz tOSHL Pin to Pin Skew 1.0 ns (Note 3) for HL Transitions tOSLH Pin to Pin Skew 1.0 ns (Note 3) for LH Transitions tOST Pin to Pin Skew 3.0 ns (Note 3) for HL/LH Transitions tQ/Q True/Complement 1.8 ns (Note 3) Output Skew tPS Pin (Signal) 1.8 ns (Note 3) Transition Variation Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF M i nM a xM i nM a x tS(H) Setup Time, HIGH or LOW 2.5 2.5 ns tS(L) D n to CPn 2.5 2.5 tH (H) Hold Time, HIGH or LOW 0 0 ns tH (L) D n to CPn 00 tW (H) CP n Pulse Width 3.3 3.3 ns tW (L) HIGH or LOW 3.3 3.3 (Note 4) tW (L) SDn or CDn Pulse Width 4.0 4.0 ns tREC Recovery Time 2.0 2.0 ns SDn or CDn to CPn

www.fairchildsemi.com 6 74FR74 • 74FR1074 Note 5: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL ) or LOW-to-HIGH (tOSLH ) or in opposite directions both HL and LH (tOST ). tOST is guaranteed by design. AC Operating Requirements 74FR1074 Note 6: This specification is guaranteed by design. Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max fMAX Maximum Clock Frequency 120 160 120 MHz tOSHL Pin to Pin Skew 1.5 ns (Note 5) for HL Transitions tOSLH Pin to Pin Skew 1.5 ns (Note 5) for LH Transitions tOST Pin to Pin Skew 3.5 ns (Note 5) for HL/LH Transitions tQ/Q True/Complement 2.0 ns (Note 5) Output Skew tPS Pin (Signal) 2.0 ns (Note 5) Transition Variation TA = +25°CT A = 0°C = +70°C Symbol Parameter V CC = +5.0V V CC = +5.0V Units C L = 50 pF C L = 50 pF Min Max Min Max tS(H) Setup Time, HIGH or LOW 2.0 2.0 ns tS(L) D n to CPn 2.0 2.0 tH (H) Hold Time, HIGH or LOW 0 0 ns tH (L) D n to CPn 00 tW (H) CP n Pulse Width 3.3 3.3 ns tW (L) HIGH or LOW 3.3 3.3 (Note 6) tW (L) SDn or CDn Pulse Width 4.0 4.0 ns tREC Recovery Time 2.0 2.0 ns SDn or CDn to CPn

7 www.fairchildsemi.com 74FR74 • 74FR1074 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

www.fairchildsemi.com 8 74FR74 • 74FR1074 Dual D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com