74FCT162500CTPVG

IDT74FCT162500AT RENESAS | Alldatasheet

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FAST CMOS 18-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2009 IDT74FCT162500AT/CT INDUSTRIAL TEMPERATURE RANGE FAST CMOS 18-BIT REGISTERED TRANSCEIVER DESCRIPTION: The FCT162500T 18-bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B port to A port is similar but uses OEBA, LEBA and CLKBA. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT162500T have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times–reducing the need for external series terminating resistors. The FCT162500T are plug-in replacements for the FCT16500T and ABT16500 for on-board bus interface applications. C D C DA1 LEAB CLKAB OEBA LEBA CLKBA OEAB TO 17 OTHER CHANNELS C D C D The IDT logo is a registered trademark of Integrated Device Technology, Inc. © 2009 Integrated Device Technology, Inc. DSC-5432/5 FEATURES:

• 0.5 MICRON CMOS Technology  High-speed, low-power CMOS replacement for ABT functions  Typical t SK(o) (Output Skew) < 250ps  Low input and output leakage ≤≤≤≤≤1µA (max.)  ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) V CC = 5V ±10%  Balanced Output Drivers (±24mA)  Reduced system switching noise  Typical V OLP (Output Ground Bounce) < 0.6V at V CC = 5V, TA = 25°C  Available in SSOP package FUNCTIONAL BLOCK DIAGRAM

INDUSTRIAL TEMPERATURE RANGE IDT74FCT162500AT/CT FAST CMOS 18-BIT REGISTERED TRANSCEIVER SSOP TOP VIEW PIN CONFIGURATION GND GND VCC B10 B11 GND B12 B13 VCC B14 GND CLKAB B16 B15 B17 GND B18 GND CLKBA OEAB LEAB GND VCC GND GND A10 A11 VCC A12 A18 A14 A13 A16 GND A17 LEBA A15 OEBA 3225 PIN DESCRIPTION Pin Names Description OEAB A-to-B Output Enable Input OEBA B-to-A Output Enable Input (Active LOW) LEAB A-to-B Latch Enable Input LEBA B-to-A Latch Enable Input CLKAB A-to-B Clock Input (Active LOW) CLKBA B-to-A Clock Input (Active LOW) A x A-to-B Data Inputs or B-to-A 3-State Outputs B x B-to-A Data Inputs or A-to-B 3-State Outputs Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to 7 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to V CC+0.5 V TSTG Storage Temperature –65 to +150 ° C IOUT DC Output Current –60 to +120 mA ABSOLUTE MAXIMUM RATINGS(1)(1)(1)(1)(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Output and I/O terminals for FCT162XXX. Symbol Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance V IN = 0V 3.5 6 pF COUT Output Capacitance V OUT = 0V 3.5 8 pF CAPACITANCE (TA = +25°C, F = 1.0MHz) NOTE: 1. This parameter is measured at characterization but not tested. FUNCTION TABLE(1, 4) NOTES: 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-impedance ↓ = HIGH-to-LOW Transition Inputs Outputs OEAB LEAB CLKAB Ax Bx LX X XZ HH X L L HH X HH HL ↓ LL HL ↓ HH HL H X B (2) HL L X B (3)

FAST CMOS 18-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE Symbol Parameter Test Conditions (1) Min. Typ.(2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V IIH Input HIGH Current (Input pins)(5) VCC = Max. V I = VCC —— ±1µ A Input HIGH Current (I/O pins)(5) —— ±1 IIL Input LOW Current (Input pins)(5) VI = GND — — ±1 Input LOW Current (I/O pins)(5) —— ±1 IOZH High Impedance Output Current V CC = Max. V O = 2.7V — — ±1µ A IOZL (3-State Output pins)(5) VO = 0.5V — — ±1 VIK Clamp Diode Voltage V CC = Min., IIN = –18mA — –0.7 –1.2 V IOS Short Circuit Current V CC = Max., V O = GND(3) –80 –140 –250 mA VH Input Hysteresis — — 100 — mV ICCL Quiescent Power Supply Current V CC = Max. — 5 500 µ A ICCH VIN = GND or VCC ICCZ DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: T A = –40°C to +85°C, VCC = 5.0V ±10% OUTPUT DRIVE CHARACTERISTICS NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable dev ice type. 2. Typical values are at V CC = 5.0V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is ±5µA at T A = –55°C. Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit IODL Output LOW Current V CC = 5V, VIN = VIH or VIL, VO = 1.5V(3) 60 115 200 mA IODH Output HIGH Current V CC = 5V, VIN = VIH or VIL, VO = 1.5V(3) –60 –115 –200 mA VOH Output HIGH Voltage V CC = Min. I OH = –24mA 2.4 3.3 — V VIN = VIH or VIL VOL Output LOW Voltage V CC = Min. I OH = 24mA — 0.3 0.55 V VIN = VIH or VL

INDUSTRIAL TEMPERATURE RANGE IDT74FCT162500AT/CT FAST CMOS 18-BIT REGISTERED TRANSCEIVER Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit ΔICC Quiescent Power Supply Current V CC = Max. — 0.5 1.5 mA TTL Inputs HIGH V IN = 3.4V(3) ICCD Dynamic Power Supply V CC = Max. V IN = VCC — 75 120 µ A / Current(4) Outputs Open V IN = GND MHz OEAB = OEBA = V CC or GND One Input Togging 50% Duty Cycle IC Total Power Supply Current(6) VCC = Max. V IN = VCC — 0.8 1.7 mA Outputs Open V IN = GND fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = OEBA = V CC LEAB = GND V IN = 3.4V — 1.3 3.2 One Bit Toggling V IN = GND fi = 5MHz 50% Duty Cycle VCC = Max. V IN = VCC — 3.8 6.5 (5) Outputs Open V IN = GND fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = OEBA = V CC LEAB = GND V IN = 3.4V — 8.5 20.8(5) Eighteen Bits Toggling V IN = GND fi = 2.5MHz 50% Duty Cycle POWER SUPPLY CHARACTERISTICS NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable dev ice type. 2. Typical values are at V CC = 5.0V, +25°C ambient. 3. Per TTL driven input (V IN = 3.4V). All other inputs at V CC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the I CC formula. These limits are guaranteed but not tested. 6. I C = IQUIESCENT + IINPUTS + IDYNAMIC IC = I CC + ΔICC DHNT + I CCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (I CCL, ICCH and I CCZ) ΔICC = Power Supply Current for a TTL High Input (V IN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at D H ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at f CP fi = Input Frequency Ni = Number of Inputs at fi

FAST CMOS 18-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 74FCT162500AT 74FCT162500CT Symbol Parameter Condition(1) Min.(2) Max. Min. (2) Max. Unit fMAX CLKAB or CLKBA frequency(4) CL = 50pF — 150 — 150 MHz tPLH Propagation Delay R L = 500Ω 1.5 5.1 1.5 3.8 ns tPHL Ax to Bx or Bx to Ax tPLH Propagation Delay 1.5 5.6 1.5 4.2 ns tPHL LEBA to Ax, LEAB to Bx tPLH Propagation Delay 1.5 5.6 1.5 4.4 ns tPHL CLKBA to Ax, CLKAB to Bx tPZH Output Enable Time 1.5 6 1.5 4.8 ns tPZL OEBA to Ax, OEAB to Bx tPHZ Output Disable Time 1.5 5.6 1.5 4.4 ns tPLZ OEBA to Ax, OEAB to Bx tSU Set-up Time, HIGH or LOW 3 — 2.4 — ns Ax to CLKAB, Bx to CLKBA tH Hold Time, HIGH or LOW 0 — 0 — ns Ax to CLKAB, Bx to CLKBA tSU Set-up Time HIGH or LOW Clock HIGH 3 — 2 — ns Ax to LEAB, Bx to LEBA Clock LOW 1.5 — 1.5 — ns tH Hold Time, HIGH or LOW 1.5 — 0.5 — ns Ax to LEAB, Bx to LEBA tW LEAB or LEBA Pulse Width HIGH(4) 3— 3 — n s tW CLKAB or CLKBA Pulse Width HIGH or LOW(4) 3— 3 — n s tSK(o) Output Skew(3) — 0.5 — 0.5 ns SWITCHING CHARACTERISTICS OVER OPERATING RANGE NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This parameter is guaranteed but not tested.

INDUSTRIAL TEMPERATURE RANGE IDT74FCT162500AT/CT FAST CMOS 18-BIT REGISTERED TRANSCEIVER Pulse Generator RT D.U.T. VCC VIN CL VOUT 50pF 500Ω 500Ω 7.0V 1.5V 1.5V 1.5V 1.5V DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL tSU tH tREM tSU tH PRESET CLEAR CLOCK ENABLE ETC. HIGH-LOW-HIGH PULSE LOW-HIGH-LOW PULSE tW 1.5V 1.5V SAME PHASE INPUT TRANSITION 1.5V 1.5V VOH tPLH OUTPUT OPPOSITE PHASE INPUT TRANSITION 1.5V tPLH tPHL tPHL VOL CONTROL INPUT 1.5V 3.5V OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED SWITCH OPEN VOL 0.3V 0.3V tPLZtPZL tPZH tPHZ 3.5V 1.5V 1.5V ENABLE DISABLE VOH TEST CIRCUITS AND WAVEFORMS Propagation Delay Test Circuits for All Outputs Enable and Disable Times Set-up, Hold, and Release Times Pulse Width Test Switch Open Drain Disable Low Closed Enable Low All Other Tests Open SWITCH POSITION DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to Z OUT of the Pulse Generator. NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

FAST CMOS 18-BIT REGISTERED TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE

ORDERING INFORMATION

Temp. Range XXXX Device Type XX Package PVG Shrink Small Outline Package - Green 18-Bit Registered Transceiver 74 40C to +85C

162 Double-Density, 5 Volt, Balanced Drive

Datasheet Document History 09/06/09 Pg.6 Updated the ordering information by removing the "IDT" notation and non RoHS part.

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