IDT74FCT162374AT RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 8
Technical content
FAST CMOS 16-BIT REGISTER (3-STATE) INDUSTRIAL TEMPERATURE RANGE SEPTEMBER 2009 IDT74FCT162374AT/CT/ET INDUSTRIAL TEMPERATURE RANGE FAST CMOS 16-BIT REGISTER (3-STATE) DESCRIPTION: The FCT162374T 16-bit edge-triggered D-type registers are built using advanced dual metal CMOS technology. These high-speed, low-power registers are ideal for use as buffer registers for data synchronization and storage. The Output Enable (xOE) and clock (xCLK) controls are organized to operate each device as two 8-bit registers or one 16-bit register with common clock. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT162374T has balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times–reducing the need for external series terminating resistors.The FCT162374T are plug-in replacements for the FCT16374T and ABT16374 for on-board bus interface applications. 2O1 2OE 2CLK 2D1 TO SEVEN OTHER CHANNELS C D 1OE 1CLK 1O1 1D1 TO SEVEN OTHER CHANNELS C D The IDT logo is a registered trademark of Integrated Device Technology, Inc. © 2009 Integrated Device Technology, Inc. DSC-5453/7 FEATURES:
- 0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical t SK(o) (Output Skew) < 250ps Low input and output leakage ≤≤≤≤≤1µA (max.) V CC = 5V ±10% Balanced Output Drivers: ±24mA Reduced system switching noise Typical VOLP (Output Ground Bounce) < 0.6V at V CC = 5V, TA = 25°C Available in SSOP and TSSOP packages FUNCTIONAL BLOCK DIAGRAM
INDUSTRIAL TEMPERATURE RANGE IDT74FCT162374AT/CT/ET FAST CMOS 16-BIT REGISTER (3-STATE) SSOP/ TSSOP TOP VIEW PIN CONFIGURATION 1O1 GND 1O3 VCC 1OE GND 2O2 GND VCC GND 1O2 1O4 1O5 1O6 1O7 1O8 2O1 2O3 2O4 2O5 2O7 2O8 2O6 2OE 1CLK 1D1 1D2 GND 1D3 1D4 VCC 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 VCC 2D5 2D7 2D8 2D6 2CLK GND GND GND Symbol Description Max Unit VTERM(2) Terminal Voltage with Respect to GND –0.5 to 7 V VTERM(3) Terminal Voltage with Respect to GND –0.5 to V CC+0.5 V TSTG Storage Temperature –65 to +150 ° C IOUT DC Output Current –60 to 120 mA ABSOLUTE MAXIMUM RATINGS(1)(1)(1)(1)(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FCT162XXX Output and I/O terminals. 3. Output and I/O terminals terminals for FCT162XXX. Symbol Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance V IN = 0V 3.5 6 pF COUT Output Capacitance V OUT = 0V 3.5 8 pF CAPACITANCE (TA = +25°C, F = 1.0MHz) NOTE: 1. This parameter is measured at characterization but not tested. Pin Names Description xDx Data Inputs xCLK Clock Inputs x O x 3-State Outputs xOE 3-State Outputs Enable Input (Active LOW) PIN DESCRIPTION NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance ↑ = LOW-to-HIGH transition Inputs Outputs Function xDx xCLK x OE xOx Hi-Z X L H Z XH H Z Load L ↑ LL Register H ↑ LH L ↑ HZ H ↑ HZ FUNCTION TABLE(1)
FAST CMOS 16-BIT REGISTER (3-STATE) INDUSTRIAL TEMPERATURE RANGE Symbol Parameter Test Conditions (1) Min. Typ.(2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2 — — V VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V IIH Input HIGH Current (Input pins)(5) VCC = Max. V I = VCC —— ±1µ A Input HIGH Current (I/O pins)(5) —— ±1 IIL Input LOW Current (Input pins)(5) VI = GND — — ±1µ A Input LOW Current (I/O pins)(5) —— ±1 IOZH High Impedance Output Current V CC = Max. V O = 2.7V — — ±1µ A IOZL (3-State Output pins)(5) VO = 0.5V — — ±1 VIK Clamp Diode Voltage V CC = Min., IIN = –18mA — –0.7 –1.2 V IOS Short Circuit Current V CC = Max., V O = GND(3) –80 –140 –250 mA VH Input Hysteresis — — 100 — mV ICCL Quiescent Power Supply Current V CC = Max. — 5 500 µ A ICCH VIN = GND or VCC ICCZ DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: T A = –40°C to +85°C, VCC = 5.0V ±10% Symbol Pa rameter Test Conditions (1) Min Typ. (2) Max. Unit IODL Output LOW Current V CC = 5V, VIN = VIH or VIL, VO = 1.5V(3) 60 115 200 mA IODH Output HIGH Current V CC = 5V, VIN = VIH or VIL, VO = 1.5V(3) –60 –115 –200 mA VOH Output HIGH Voltage V CC = Min I OH = –24mA 2.4 3.3 — V VIN = VIH or VIL VOL Output LOW Voltage V CC = Min I OL = 24mA — 0.3 0.55 V VIN = VIH or VIL OUTPUT DRIVE CHARACTERISTICS NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable dev ice type. 2. Typical values are at V CC = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is ±5µA at T A = –55°C.
INDUSTRIAL TEMPERATURE RANGE IDT74FCT162374AT/CT/ET FAST CMOS 16-BIT REGISTER (3-STATE) Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit ΔICC Quiescent Power Supply Current V CC = Max. — 0.5 1.5 mA TTL Inputs HIGH V IN = 3.4V(3) ICCD Dynamic Power Supply V CC = Max. V IN = VCC — 60 100 µ A / Current(4) Outputs Open V IN = GND MHz xOE = GND One Input Togging 50% Duty Cycle IC Total Power Supply Current(6) VCC = Max. V IN = VCC — 0.6 1.5 mA Outputs Open V IN = GND fCP = 10MHz 50% Duty Cycle V IN = 3.4V — 1.1 3 xOE = GND V IN = GND fi = 5MHz 50% Duty Cycle One Bit Toggling VCC = Max. V IN = VCC — 3 5.5 (5) Outputs Open V IN = GND fCP = 10MHz 50% Duty Cycle xOE = GND V IN = 3.4V — 7.5 19 (5) Sixteen BitsTogging V IN = GND fi = 2.5MHz 50% Duty Cycle POWER SUPPLY CHARACTERISTICS NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable dev ice type. 2. Typical values are at V CC = 5.0V, +25°C ambient. 3. Per TTL driven input (V IN = 3.4V). All other inputs at V CC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the I CC formula. These limits are guaranteed but not tested. 6. I C = IQUIESCENT + IINPUTS + IDYNAMIC IC = I CC + ΔICC DHNT + I CCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (I CCL, ICCH and I CCZ) ΔICC = Power Supply Current for a TTL High Input (V IN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at D H ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at f CP fi = Input Frequency Ni = Number of Inputs at fi
FAST CMOS 16-BIT REGISTER (3-STATE) INDUSTRIAL TEMPERATURE RANGE 74FCT162374AT 74FCT162374CT 74FCT162374ET tPLH Propagation Delay C L = 50pF 2 6.5 2 5.2 1.5 3.7 ns tPHL xCLK to xOx R L = 500Ω tPZL tPLZ tSU Set-up Time HIGH or LOW, xDx to xCLK 2 — 2 — 1.5 — ns tH Hold Time HIGH or LOW, xDx to xCLK 1.5 — 1.5 — 0 — ns tW xCLK Pulse Width HIGH or LOW 5 — 5 — 3 (4) —n s tSK(o) Output Skew(3) — 0.5 — 0.5 — 0.5 ns SWITCHING CHARACTERISTICS OVER OPERATING RANGE NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 4. This limit is guaranteed but not tested.
INDUSTRIAL TEMPERATURE RANGE IDT74FCT162374AT/CT/ET FAST CMOS 16-BIT REGISTER (3-STATE) Pulse Generator RT D.U.T. VCC VIN CL VOUT 50pF 500Ω 500Ω 7.0V 1.5V 1.5V 1.5V 1.5V DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL tSU tH tREM tSU tH PRESET CLEAR CLOCK ENABLE ETC. HIGH-LOW-HIGH PULSE LOW-HIGH-LOW PULSE tW 1.5V 1.5V SAME PHASE INPUT TRANSITION 1.5V 1.5V VOH tPLH OUTPUT OPPOSITE PHASE INPUT TRANSITION 1.5V tPLH tPHL tPHL VOL CONTROL INPUT 1.5V 3.5V OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED SWITCH OPEN VOL 0.3V 0.3V tPLZtPZL tPZH tPHZ 3.5V 1.5V 1.5V ENABLE DISABLE VOH TEST CIRCUITS AND WAVEFORMS Propagation Delay Test Circuit for All Outputs Enable and Disable Times Set-up, Hold and Release Times Pulse Width Test Switch Open Drain Disable Low Closed Enable Low All Other Tests Open SWITCH POSITION DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to Z OUT of the Pulse Generator. NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
FAST CMOS 16-BIT REGISTER (3-STATE) INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
Temp. Range XXXX Device Type XX Package PVG PAG Shrink Small Outline Package - Green Thin Shrink Small Outline Packag - Green 16-Bit Register (3-State) 74 40C to +85C
162 Double-Density, 5 Volt, Balanced Drive
Datasheet Document History 09/06/09 Pg.6 Updated the ordering information by removing the "IDT" notation and non RoHS part.
© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.