74F899 FAIRCHILD | Alldatasheet

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■ Latchable transceiver with output sink of 24 mA at the A-bus and 64 mA at the B-bus ■ Option to select generate parity and check or “feed-through” data/parity in directions A-to-B or B-to-A ■ Independent latch enables for A-to-B and B-to-A directions ■ Select pin for ODD/EVEN parity ■ ERRA and ERRB output pins for parity checking ■ Ability to simultaneously generate and check parity ■ May be used in systems applications in place of the 74F543 and 74F280 ■ May be used in system applications in place of the 74F657 and 74F373 (no need to change T/R to check parity) Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignment for SOIC Pin Assignment for PCC Logic Symbol Order Number Package Number Package Description 74F899SC M28B 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F899QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

www.fairchildsemi.com 2 74F899 Input Loading/Fan-Out Pin Descriptions Functional Description The 74F899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions.

  • Bus A (B) communicates to Bus B (A), parity is gener- ated and passed on to the B (A) Bus as BPAR (APAR). If LEB (LEA) is HIGH and the Mode Select (SEL ) is LOW, the parity generated from B[0:7] (A[0:7]) can be checked and monitored by ERRB (ERRA).
  • Bus A (B) communicates to Bus B (A) in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode (can be used as an interrupt to signal a data/parity bit error to the CPU).
  • Independent Latch Enables (LEA and LEB) allow other permutations of generating/checking (see Function Table). HIGH/LOW Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output IOH /IOL A0–A7 Data Inputs/ 1.0/1.0 20 µA/−0.6 mA Data Outputs 150/40 −3 mA/24 mA B0–B7 Data Inputs/ 1.0/1.0 20 µA/−0.6 mA Data Outputs 600/106.6 −12 mA/64 mA APAR A Bus Parity 1.0/1.0 20 µA/−0.6 mA Input/Output 150/40 −3 mA/24 mA BPAR B Bus Parity 1.0/1.0 20 µA/−0.6 mA Input/Output 600/106.6 −12 mA/64 mA ODD/EVEN Parity Select Input 1.0/1.0 20 µA/−0.6 mA GBA , GAB Output Enable Inputs 1.0/1.0 20 µA/−0.6 mA SEL Mode Select Input 1.0/1.0 20 µA/−0.6 mA LEA, LEB Latch Enable Inputs 1.0/1.0 20 µA/−0.6 mA ERRA , ERRB Error Signal Outputs 50/33.3 −1 mA/20 mA Pin Names Description A0–A7 A Bus Data Inputs/Data Outputs B0–B7 B Bus Data Inputs/Data Outputs APAR, BPAR A and B Bus Parity Inputs ODD/EVEN ODD/EVEN Parity Select, Active LOW for EVEN Parity GBA , GAB Output Enables for A or B Bus, Active LOW SEL Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode LEA, LEB Latch Enables for A and B Latches, HIGH for Transparent Mode ERRA , ERRB Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs

3 www.fairchildsemi.com 74F899 Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note 1: O/E = ODD/EVEN Functional Block Diagram Inputs Operation GAB GBA SEL LEA LEB H H X X X Busses A and B are 3-STATE. HL L L H Generates parity from B[0:7] based on O/E (Note 1). Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. H L L H H Generates parity from B[0:7] based on O/E . Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. HL L X L Generates parity from B latch data based on O/E. Generated parity → APAR. Generated parity checked against latched BPAR and output as ERRB. HL H X H B P A R / B [ 0 : 7 ] → APAR/A0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. H L H H H BPAR/B[0:7] → APAR/A[0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. L H L H L Generates parity for A[0:7] based on O/E . Generated parity → BPAR. Generated parity checked against APAR and output as ERRA. L H L H H Generates parity from A[0:7] based on O/E . Generated parity → BPAR. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. L H L L X Generates parity from A latch data based on O/E . Generated parity → BPAR. Generated parity checked against latched APAR and output as ERRA. LH H H L A P A R / A [ 0 : 7 ] → BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. L H H H H APAR/A[0:7] → BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB.

www.fairchildsemi.com 4 74F899 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) Twice the Rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.5 I OH = −1 mA Voltage 10% V CC 2.4 I OH = −3 mA 10% V CC 2.0 V I OH = −15 mA (Bn, BPAR) 5% VCC 2.7 I OH = −1 mA 5% VCC 2.7 I OH = −3 mA VOL Output LOW 10% V CC 0.5 I OL = 20 mA Voltage (An, APAR, ERRA, ERRB) 5% VCC 0.55 V I OL = 24 mA (An, APAR, ERRA, ERRB) 10% V CC 0.55 I OL = 64 mA (Bn, BPAR) VTH Input Threshold Voltage 1.45 V ±0.1V, Sweep Edge Rate must be > 1V/50 ns VOLV Negative Ground Bounce 1.0 V Observed on “quiet” output during Voltage simultaneous switching of remaining outputs VOLP Positive Ground Bounce 1.0 V Observed on “quiet” output during Voltage simultaneous switching of remaining outputs IIL Input Low Current −0.6 mA Max V IN = 0.5V IIH Input HIGH 5.0 µAM a x V IN = 2.7V Current IBVI Input HIGH Current 7.0 µAM a x VIN = 7.0V Breakdown Test (ODD/EVEN , GBA, GAB, SEL, LEA, LEB) IBVIT Input HIGH Current 0.5 mA Max VIN = 5.5V Breakdown (I/O) (An, Bn, APAR , BPAR ) ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input Low Current −0.6 mA Max V IN = 0.5V IIH+ Output Leakage Current 70 µAM a x VI/O = 2.7V IOZH Current (An, Bn, APAR, BPAR)

11 www.fairchildsemi.com 74F899 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M28B

www.fairchildsemi.com 12 74F899 9-Bit Latchable Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com