74F8962 PHILIPS | Alldatasheet

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Philips Semiconductors FAST Products Product specification 74F8962/89639-Bit latched bidirectional Futurebus transceivers (open-collector) 1March 11, 1993 853–1425 09230

FEATURES

  • Octal latched transceiver
  • Drives heavily loaded backplanes with equivalent load impedances down to 10Ω
  • High drive (100mA) open collector drivers on B port
  • Reduced voltage swing (1 volt) produces less noise and reduces power consumption
  • High speed operation enhances performance of backplane buses and facilitates incident wave switching
  • Compatible with IEEE 896 futurebus standards
  • Built–in precision band–gap reference provides accurate receiver thresholds and improved noise immunity
  • Multiple GND pins minimize ground bounce
  • Glitch–free power up/power down operation

DESCRIPTION

The 74F8962 and 74F8963 are octal bidirectional latched transceivers and are intended to provide the electrical interface to a high performance wired-OR bus. The B port inverting drivers are low-capacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a 150mV threshold region. The B port interfaces to ‘Backplane Transceiver Logic’ (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading. Incident wave switching to 9Ω is guaranteed. The voltage swing is much less for BTL, so is its receiver threshold region, therefore noise margins are excellent. BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane. The 74F8962 and 74F8963 A ports have TTL 3-state drivers and TTL receivers with a latch function. The 74F8963 is the non-inverting version of 74F8962. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT( TOTAL) 74F8962 6.5ns 90mA 74F8963 5.5ns 90mA

ORDERING INFORMATION

DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 44–pin Quad Flat Pack1 N74F8962Y , N74F8963Y 44–pin Plastic Leaded Chip Carrier N74F8962A, N74F8963A Note to ordering information 1. Flatpack package is not available at this time. INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW AI0 – AI8 PNP latched inputs 1.0/0.167 20µA/100µA B0 – B8 Data inputs with threshold circuitry 5.0/0.167 100µA/100µA OEAB , OEBA Output enable inputs (active low) 1.0/0.033 20µA/20µA LEAB , LEBA Latch enable inputs (active low) 1.0/0.033 20µA/20µA AO0 – AO8 3–state outputs 150/40 3mA/24mA B0 – B8 Open collector outputs OC/166.7 OC/100mA Notes to input and output loading and fan out table 1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. 2. OC = Open collector.

Philips Semiconductors FAST Products Product specification 74F8962/89639-Bit latched bidirectional Futurebus transceivers (open-collector) March 11, 1993 2 PIN CONFIGURATION FLATPACK AND PLCC IEC/IEEE SYMBOL 74F8962 6 5 4 3 2 1 2422 23212019 AO0AI1AO1GND AI0 VCC OEBA AO7AI7GND 2826 2725 43 42 41 40 LEBA BO GND B1 2917 AI2 AO2 A13 AO3 AI4 GND AO4 AI5 AO5 AI6 AO6 AI8 AO8 VCC LEAB OEAB B8 GND B7 GND GND GND GND GND GND 74F8962 EN1 EN2 EN3 EN4 4 3D PIN DESCRIPTION SYMBOL PINS TYPE NAME AND FUNCTION AI0 – AI8 2, 4, 7, 9, 11, 14, 16, 19, 21Input PNP latched inputs. B0 – B8 42, 40, 38, 36, 34, 32, 30, 28, 26I/O Data input / open collector output, high current drives. OEAB 25 Input Output enable input. Enables the B outputs when low. OEB A 44 Input Output enable input. Enables the A outputs when high. LEAB 24 Input Latch enable input. Enables the AB latches low. LEBA 43 Input Latch enable input. Enables the BA latches low. AO0 – AO8 3, 5, 8, 10, 13, 15, 17, 20, 22Output TTL 3–state outputs. GND 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41Ground Grounds VCC 1, 23 Power Positive supply voltages

Philips Semiconductors FAST Products Product specification 74F8962/89639-Bit latched bidirectional Futurebus transceivers (open-collector) March 11, 1993 3 LOGIC SYMBOL FOR 74F8962 OEBA OEAB LEAB LEBA AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8 42 40 38 B0 B1 B2 36 34 32 30 28 26 B6 B7 B8B3 B4 B5 VCC = Pin 1, 23 GND = Pin 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41 74F8962 2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 21 22 LOGIC SYMBOL FOR 74F8963 OEBA OEAB LEAB LEBA AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8 42 40 38 B0 B1 B2 36 34 32 30 28 26 B6 B7 B8B3 B4 B5 74F8963 VCC = Pin 1, 23 GND = Pin 6, 12, 18, 27, 29, 31, 33, 35, 37, 39, 41 2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 21 22

Philips Semiconductors FAST Products Product specification 74F8962/89639-Bit latched bidirectional Futurebus transceivers (open-collector) March 11, 1993 4 LOGIC DIAGRAM Data E Q VCC = Pin 1, 23 GND = Pin 6, 12, 18, 27, 29, 31, 33, 37, 39, 41 Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8 OEAB LEBA LEAB OEBA Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q Data E Q AI0 AO0 AI1 AO1 AI2 AO2 AI3 AO3 AI4 AO4 AI5 AO5 AI6 AO6 AI7 AO7 AI8 AO8 OEAB LEBA LEAB OEBA 74F8962 74F8963 Data E

Philips Semiconductors FAST Products Product specification 74F8962/89639-Bit latched bidirectional Futurebus transceivers (open-collector) March 11, 1993 5 FUNCTION TABLE FOR 74F8962 INPUTS LATCH STATES OUTPUTS OPERATING MODE AIn Bn* LEAB LEBA OEAB OEBA AB BA AOn Bn H H L L H H H H Z X L L L L H H L L Z X B and AO disabled X X H H H H Qn Qn Z X H – L X L H H Qn Z L AO 3–state, transparent data from AI to B L – L X L H L Qn Z H X H X L H L Qn H L X B disabled, transparent data from B to AO X L X L H L Qn L H X X X H X L H Qn Qn Z Q n AO 3–state, latched data to B X X X H H L Qn Qn Qn X B disabled, latched to AO X X H H L L Qn Qn Qn Qn Latched state to AO and B H – L L L L H L H L Read back from AI to B to AO L – L L L L L H L H (both latches transparent) Notes to function table for 74F8962 1. H = High voltage level 2. L = Low voltage level 3. X = Don’t care 4. – = Input not externally driven 5. Z = High impedance ”off’ state 6. Qn = High or low voltage level one setup time prior to the low–to–high LEXX transition. 7. H**= Goes to level of pullup voltage. 8. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state. FUNCTION TABLE FOR 74F8963 INPUTS LATCH STATES OUTPUTS OPERATING MODE AIn Bn* LEAB LEBA OEAB OEBA AB BA AOn Bn H H L L H H L L Z X L L L L H H H H Z X B and AO disabled X X H H H H Q n Q n Z X H – L X L H L Q n Z H AO 3–state, transparent data from AI to B L – L X L H H Q n Z L X H X L H L Q n L H X B disabled, transparent data from B to AO X L X L H L Q n H L X X X H X L H Q n Q n Z Q n AO 3–state, latched data to B X X X H H L Q n Q n Qn X B disabled, latched to AO X X H H L L Q n Q n Qn Qn Latched state to AO and B H – L L L L L L H H Read back from AI to B to AO L – L L L L H L L L (both latches transparent) Notes to function table for 74F8963 1. H = High voltage level 2. L = Low voltage level 3. X = Don’t care 4. – = Input not externally driven 5. Z = High impedance ”off” state 6. Qn = High or low voltage level one setup time prior to the low–to–high LEXX transition. 7. H= Goes to level of pullup voltage. 8. B* = Precaution should be taken to insure B inputs do not float. If they do they are equal to low state.

Philips Semiconductors FAST Products Product specification 74F8962/89639-Bit latched bidirectional Futurebus transceivers (open-collector) March 11, 1993 6 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage OEBA , OEAB, LEBA, LEAB –0.5 to +7.0 V AI0 – AI8, B0 – B8 –0.5 to +5.5 V IIN Input current –40 to +5 mA VOUT Voltage applied to output in high output state –0.5 to VCC V IOUT Current applied to output in low output state AO0 – AO8 48 mA B0 – B8 200 mA Tamb Operating free air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIH High–level input voltage Except B0 – B8 2.0 V B0 – B8 1.62 V VIL Low–level input voltage Except B0 – B8 0.8 V B0 – B8 1.47 V IIk Input clamp current –18 mA IOH High–level output current AO0 – AO8 –3 mA IOL Low–level output current AO0 – AO8 24 mA B0 – B8 100 mA Tamb Operating free air temperature range 0 +70 °C

Philips Semiconductors FAST Products Product specification 74F8962/89639-Bit latched bidirectional Futurebus transceivers (open-collector) March 11, 1993 7 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST LIMITS UNIT CONDITIONS 1 MIN TYP 2 MAX IOH High-level output current B0 – B8 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA IOFF Power-off output current B0 – B8 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA VOH High-level output voltageAO0 – AO84 VCC = MAX, VIL = MAX, VIH = MIN, IOH = –3mA 2.5 VCC V AO0 – AO84 VCC = MIN, IOL = 24mA 0.50 V VOL Low-level output voltage B0 – B8 VIL = MAX IOL = 100mA 0.75 1.0 1.10 V VIH = MIN IOL = 4mA 0.40 V VIK Input clamp voltage VCC = MIN, II = IIK -1.2 V II Input current at maximum input voltage OEAB , OEBA, LEAB , LEBA, AI0 – AI8 VCC = MAX, VI = 7.0V 100 µA B0 – B8 VCC = MAX, VI = 5.5V 1 mA IIH High-level input current OEAB , OEBA, LEAB , LEBA, AI0 – AI8 VCC = MAX, VI = 2.7V 20 µA B0 – B8 VCC = MAX, VI = 2.1V 100 µA IIL Low-level input current OEAB , OEBA, LEAB , LEBA, AI0 – AI8 VCC = MAX, VI = 0.5V –100 µA B0 – B8 VCC = MAX, VI = 0.3V –100 µA IOZH Off state output current, high-level voltage appliedAO0 – AO8 VCC = MAX, VO = 2.7V 50 µA IOZL Off state output current, low-level voltage applied VCC = MAX, VI = 0.5V –50 µA IOS Short circuit output AO0 – AO8 ’F896074F8962 VCC = MAX, Bn = 1.3V, OEBA = 0.8V, OEAB = 2.7V -60 -150 mA current3 only 74F8963 VCC = MAX, Bn = 1.8V, OEBA = 0.8V, OEAB = 2.7V ICCH VCC = MAX 80 110 mA ICC Supply current (total) ICCL VCC = MAX, VIL = 0.5V 105 145 mA ICCZ 80 110 mA NOTES TO DC ELECTRICAL CHARACTERISTICS 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are for VIH = 1.8V and VIL = 1.3V.

Philips Semiconductors FAST Products Product specification 74F8962/89639-Bit latched bidirectional Futurebus transceivers (open-collector) March 11, 1993 8 AC ELECTRICAL CHARACTERISTICS FOR 74F8962 A PORT LIMITS Tamb = +25°C Tamb = 0°C to +70°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% VCC = +5.0V ± 5% UNIT CONDITION C L = 50pF, R L = 500Ω C L = 50pF, R L = 500Ω C L = 50pF, R L = 500Ω MIN TYP MAX MIN MAX MIN MAX tPLH tPHL Propagation delay Bn to AOn Waveform 1, 2 5.0 3.5 7.0 5.5 10.0 8.5 4.5 3.5 11.0 8.5 4.5 3.5 10.5 8.5 ns tPLH tPHL Propagation delay LEBA to AOn Waveform 1, 2 5.5 4.5 7.0 6.5 10.0 9.5 5.0 4.5 10.0 9.5 5.0 4.5 10.0 9.5 ns tPZH tPZL Output enable time to high or low, OEBA to AOn Waveform 5, 6 7.5 8.5 9.5 10.5 12.5 13.0 6.5 7.5 13.5 14.5 6.5 7.5 13.0 13.5 ns tPHZ tPLZ Output disable from high or low, OEBA to AOn Waveform 5, 6 3.5 4.5 5.5 6.5 8.5 9.5 2.5 4.0 10.0 10.0 2.5 4.0 9.0 9.5 ns tsk(o) Skew between receivers in same package Waveform 4 1.5 2.0 4.0 4.0 ns B PORT LIMITS Tamb = +25°C Tamb = 0°C to +70°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% VCC = +5.0V ± 5% UNIT CONDITION C D = 30pF, R U = 9Ω C D = 30pF, R U = 9Ω C D = 30pF, R U = 9Ω MIN TYP MAX MIN MAX MIN MAX tPLH tPHL Propagation delay AIn to Bn Waveform 1, 2 3.5 4.0 5.5 6.0 8.5 9.5 3.0 3.5 9.0 10.5 3.0 3.5 9.0 10.0 ns tPLH tPHL Propagation delay LEAB to Bn Waveform 1, 2 4.0 5.0 6.0 7.0 8.5 10.5 3.5 5.0 9.5 10.5 3.5 5.0 9.5 10.5 ns tPLH tPHL Output enable/disable time OEBA to Bn Waveform 1 3.5 3.0 5.0 4.0 8.0 8.0 3.0 2.5 8.5 8.5 3.0 2.5 8.0 8.5 ns tTLH tTHL Transition time, Bn port 10% to 90%, 90% to 10% Test circuit and waveforms 1.0 1.0 1.2 2.0 1.6 2.5 1.0 1.0 2.5 3.5 1.0 1.0 2.5 3.5 ns tsk(o) Skew between drivers in same package Waveform 4 0.5 2.5 3.0 3.0 ns AC SETUP REQUIREMENTS FOR 74F8962 LIMITS Tamb = +25°C Tamb = 0°C to +70°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% VCC = +5.0V ± 5% UNIT CONDITION C L = 50pF, R L = 500Ω C L = 50pF, R L = 500Ω C L = 50pF, R L = 500Ω MIN TYP MAX MIN MAX MIN MAX tsu(H) tsu(L) Setup time, high or low AIn to LEAB Waveform 3 3.0 1.0 3.5 2.0 3.0 1.5 ns th(H ) th(L) Hold time, high or low AIn to LEAB Waveform 3 3.0 0.0 3.5 0.0 3.0 0.0 ns tsu(H) tsu(L) Setup time, high or low Bn to LEBA Waveform 3 2.0 1.0 2.5 1.0 2.0 1.0 ns th(H) th(L) Hold time, high or low Bn to LEBA Waveform 3 3.0 1.5 3.5 2.0 3.0 2.0 ns tw (L) LEAB or LEBA pulse width, lowWaveform 3 4.5 4.5 4.5 ns

Philips Semiconductors FAST Products Product specification 74F8962/89639-Bit latched bidirectional Futurebus transceivers (open-collector) March 11, 1993 9 AC ELECTRICAL CHARACTERISTICS FOR 74F8963 A PORT LIMITS Tamb = +25°C Tamb = 0°C to +70°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% VCC = +5.0V ± 5% UNIT CONDITION C L = 50pF, R L = 500Ω C L = 50pF, R L = 500Ω C L = 50pF, R L = 500Ω MIN TYP MAX MIN MAX MIN MAX tPLH tPHL Propagation delay Bn to AOn Waveform 1, 2 3.5 2.5 5.5 4.0 8.0 7.0 3.0 2.0 9.0 7.5 3.0 2.0 8.0 7.5 ns tPLH tPHL Propagation delay LEBA to AOn Waveform 1, 2 6.0 4.0 7.5 5.5 10.0 8.5 5.0 3.5 11.5 9.0 5.0 3.5 10.0 8.5 ns tPZH tPZL Output enable time to high or low, OEBA to AOn Waveform 5, 6 9.0 10.0 11.0 12.0 15.0 16.0 8.5 9.0 16.5 18.0 8.5 9.0 15.5 16.5 ns tPHZ tPLZ Output disable time from high or low, OEBA to AOn Waveform 5, 6 4.0 5.5 6.0 7.0 9.0 11.0 3.0 5.0 10.5 12.0 3.0 5.0 9.5 11.0 ns tsk(o) Skew between receivers in same package Waveform 4 1.5 2.0 4.0 4.0 ns B PORT LIMITS Tamb = +25°C Tamb = 0°C to +70°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% VCC = +5.0V ± 5% UNIT CONDITION C D = 30pF, R U = 9Ω C D = 30pF, R U = 9Ω C D = 30pF, R U = 9Ω MIN TYP MAX MIN MAX MIN MAX tPLH tPHL Propagation delay AIn to Bn Waveform 1, 2 2.0 2.0 4.0 3.5 6.5 6.5 1.5 1.5 7.0 6.5 2.0 2.0 7.0 6.5 ns tPLH tPHL Propagation delay LEAB to Bn Waveform 1, 2 3.5 2.5 5.0 4.0 8.0 7.0 3.0 2.0 8.5 8.0 3.5 2.5 8.5 8.0 ns tPLH tPHL Output enable/disable time OEBA to Bn Waveform 1 3.5 3.0 5.5 5.0 9.0 7.5 2.5 2.5 9.5 8.5 2.5 2.5 9.0 8.0 ns tTLH tTHL Transition time, Bn port 10% to 90%, 90% to 10% Test circuit and waveforms 1.0 1.0 1.2 2.0 1.6 2.5 1.0 1.0 2.5 3.5 1.0 1.0 2.5 3.5 ns tsk(o) Skew between drivers in same package Waveform 4 0.5 2.0 3.0 3.0 ns AC SETUP REQUIREMENTS FOR 74F8963 LIMITS Tamb = +25°C Tamb = 0°C to +70°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% VCC = +5.0V ± 5% UNIT CONDITION C L = 50pF, R L = 500Ω C L = 50pF, R L = 500Ω C L = 50pF, R L = 500Ω MIN TYP MAX MIN MAX MIN MAX tsu(H) tsu(L) Setup time, high or low AIn to LEAB Waveform 3 4.0 1.0 4.5 1.5 4.0 1.0 ns th(H ) th(L) Hold time, high or low AIn to LEAB Waveform 3 2.5 0.0 3.0 0.0 2.5 0.0 ns tsu(H) tsu(L) Setup time, high or low Bn to LEBA Waveform 3 2.0 1.0 2.5 1.0 2.0 1.0 ns th(H) th(L) Hold time, high or low Bn to LEBA Waveform 3 2.5 1.0 3.0 1.5 3.0 1.0 ns tw (L) LEAB or LEBA pulse width, lowWaveform 3 4.5 5.5 5.5 ns

Philips Semiconductors FAST Products Product specification 74F8962/89639-Bit latched bidirectional Futurebus transceivers (open-collector) March 11, 1993 10 AC WAVEFORMS VMVM VMVM Waveform 1. Propagation delay for data or output enable or latch enable to output W aveform 3. Data setup and hold times and LEAB/LEBA pulse widths W aveform 5. 3–state output enable time to high level and output disable time from high level W aveform 6. 3-state output enable time to low level and output disable time from low level VM VM VM VM VM VM tsu(L) tsu(H)th(L) th(H) VM VM VM tPHZtPZH VOH -0.3V VM VM VM tPLZtPZL VOL +0.3V An OEAB An AOn, Bn AIn, Bn, LEAB , LEBA OEAB tPLH tPHL VM tw (L) VMVM VMVM Waveform 2. Propagation delay for data or latch enable to output An, Bn tPHL tPLH AIn, Bn, LEAB , LEBA AIn, Bn LEAB , LEBA OEAB Waveform 4. Output skew VM VM tsk(o) AOn, Bn AOn, Bn NOTES TO AC WAVEFORMS 1. For all waveforms, VM = 1.5V. 2. The shaded areas indicate when the input is permitted to change for predictable output performance. TEST CIRCUITS AND WAVEFORMS tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) Low V Low V tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tw tTLH tTHL Input pulse definition VCC family 74F D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test circuit for 3–state outputs on A port DEFINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R U = Pull up resistor; see AC electrical characteristics for value. C D = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = T ermination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude VM R L 7.0V VCC D.U.T.PULSE GENERATOR C DR T VIN VOUT Test circuit for outputs on B port R U 7.0V Low V SWITCH POSITION TEST SWITCH closed openAll other tPLZ , tPZL