74F8960

74F8960 PHILIPS | Alldatasheet

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Philips Semiconductors FAST Products Product specification 74F8960/74F8961Octal latched bidirectional Futurebus transceivers (3-State + open-collector) 1December 19, 1990 853-1120 01322

FEATURES

• Octal latched transceiver
• Drives heavily loaded backplanes with equivalent load impedances down to 10Ω
• High drive (100mA) open collector drivers on B port
• Reduced voltage swing (1 volt) produces less noise and reduces power consumption
• High speed operation enhances performance of backplane buses and facilitates incident wave switching
• Compatible with IEEE futurebus standards
• Built-in precision band-gap reference provides accurate receiver thresholds and improved noise immunity
• Controlled output ramp and multiple GND pins minimize ground bounce
• Glitch-free power up/down operation

DESCRIPTION

The 74F8960 and 74F8961 are octal bidirectional latched transceivers and are intended to provide the electrical interface to a high performance wired–OR bus. The B port inverting drivers are low–capacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a 100 mV threshold region and a 4ns glitch filter. The B port interfaces to ‘Backplane Transceiver Logic’ (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading. Incident switching is employed, therefore BTL propagation delays are short. Although the voltage swing is much less for BTL, so is its receiver threshold region, therefore noise margins are excellent. BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane. The 74F8960 and 74F8961 A ports have TTL 3–state drivers and TTL receivers with a latch function. A separate High–level control input (VX) is provided to limit the A side output level to a given voltage level (such as 3.3V). For 5.0V systems, VX is simply tied to VCC. The 74F8961 is the non–inverting version of 74F8960. TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT( TOTAL) 74F8960 6.5ns 80mA 74F8961 6.5ns 80mA

ORDERING INFORMATION

DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 28–pin plastic DIP (300 mil)1 N74F8960N, N748961N 28–pin PLCC1 N74F8960A, N74F8961A NOTE: Thermal mounting techiques are recommended. INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW A0 – A8 PNP latched inputs 3.5/0.117 70µA/70µA B0 – B8 Data inputs with threshold circuitry 5.0/0.167 100µA/100µA OEA A output enable input (active high) 1.0/0.033 20µA/20µA OEB 0, OEB1 B output enable inputs (active low) 1.0/0.033 20µA/20µA LE Latch enable input (active low) 1.0/0.033 20µA/20µA A0 – A7 3–state outputs 150/40 3mA/24mA B0 – B7 Open collector outputs OC/166.7 OC/100mA NOTES: 1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. 2. OC = Open collector.

Philips Semiconductors FAST Products Product specification 74F8960/74F8961Octal latched bidirectional Futurebus transceivers (3-State + open-collector) December 19, 1990 2 PIN CONFIGURATION PIN CONFIGURATION PLCC LOGIC SYMBOL 10 19 OEA GND VCC VX OEB 1 OEB 0 OEB1 OEB0 OEA LE 3 5 6 A0 A1 A2 GND 4 3 2 1 28 27 1816 17151413 PLCC GND 14 15 GND GND GND GND LE GND VCCOEAA0GND LE B0 B1 GND GND GNDOEB 1OEB2 B7VXA7A6 7 9 1012 13 A6 A7A3 A4 A5 27 26 24 B0 B1 B2 23 21 20 19 17 B6 B7B3 B4 B5 VCC = Pin 1, VX = Pin 14 GND = Pin 4, 8, 11, 18, 22, 25 74F8960 74F8960 74F8960 PIN CONFIGURATION PIN CONFIGURATION PLCC LOGIC SYMBOL

16 OEB1

VCC = Pin 1, VX = Pin 14 GND = Pin 4, 8, 11, 18, 22, 25 74F8961 74F8961 74F8961 10 19 OEA GND VCC VX OEB 1 OEB 0 14 15 GND GND GND GND LE GND GND 4 3 2 1 28 27 1816 17151413 PLCC GND VCCOEAA0GND LE B0 B1 GND GND GNDOEB 1OEB2 B7VXA7A6

Philips Semiconductors FAST Products Product specification 74F8960/74F8961Octal latched bidirectional Futurebus transceivers (3-State + open-collector) December 19, 1990 3 IEC/IEEE SYMBOL FOR 74F8960 IEC/IEEE SYMBOL FOR 74F8961 74F8960 74F8961 3 2 EN2 EN3 3 2 EN2 EN3 PIN DESCRIPTION SYMBOL PINS TYPE NAME AND FUNCTION A0 – A7 3, 5, 6, 7, 9, 10, 12, 13I/O PNP latched input/3–state output (with VX control option) B0 – B7 27, 26, 24, 23, 21, 20, 19, 17I/O Data input with special threshold circuitry to reject noise/ open collector output, high current drive OEB 0 15 Input Enables the B outputs when both pins are low OEB 1 16 Input Enables the A outputs when high LE 28 Input Latched when high (a special feature is buillt in for proper enabling times) VX 14 Input Clamping voltage keeping VOH from rising above VX (VX = Vcc for normal use)

Philips Semiconductors FAST Products Product specification 74F8960/74F8961Octal latched bidirectional Futurebus transceivers (3-State + open-collector) December 19, 1990 4 LOGIC DIAGRAM LE OEB0 Data Q 273 LE OEA VCC = Pin 1, VX = Pin 14, GND = Pin 4, 8, 11, 18, 22, 25 LE B1 Data Q 265 A1 LE B2 Data Q 246 A2 LE B3 Data Q 237 A3 LE B4 Data Q 219 A4 LE B5 Data Q 2010 A5 LE B6 Data Q 1912 A6 LE B7 Data Q 1713 A7 OEB 1 LE OEB0 Data Q 273 LE OEA LE B1 Data Q 265 A1 LE B2 Data Q 246 A2 LE B3 Data Q 237 A3 LE B4 Data Q 219 A4 LE B5 Data Q 2010 A5 LE B6 Data Q 1912 A6 LE B7 Data Q 1713 A7 OEB 1 74F986174F9860

Philips Semiconductors FAST Products Product specification 74F8960/74F8961Octal latched bidirectional Futurebus transceivers (3-State + open-collector) December 19, 1990 5 FUNCTION TABLE FOR 74F8960 INPUTS LATCH OUTPUTS OPERATING MODE An Bn* LE OEA OEB OEB STATE An Bn H X L L L L H Z L A 3–state, data from A to B L X L L L L L Z H X X H L L L Qn Z Q n A 3–state, latched data to B – – L H L L (1) (1) (1) Feedback: A to B, B to A – H H H L L H (2) H Z(2) Preconditioned latch enabling data transfer from B to A – L H H L L H (2) L Z(2) – – H H L L Qn Q n Q n Latch state to A and B H X L L H X H Z Z l X L L H X l Z Z B and A 3–state X X H L H X Qn Z Z – H L H H X H H Z – L L H H H L L Z B 3–state, data from B to A – H H H H H Qn H Z – L H H H H Qn L Z H X L L X H H Z Z l X L L X H l Z Z B and A 3–state X X H L X H Qn Z Z – H L H X H H H Z – L L H X H L L Z B 3–state, data from B to A – H H H X H Qn H Z – L H H X H Qn L Z NOTES: 1. H = High–voltage level 2. L = Low–voltage level 3. X = Don’t care 4. – = Input not externally driven 5. Z = High impedance (off) state 6. Qn = High or low voltage level one setup time prior to the low–to–high LE transition. 7. (1) =Condition will cause a feedback loop path: A to B and B to A. 8. (2) =The latch must be preconmditioned such that B inputs may assume a high or low level while OEB0 and OEB1 are low and LE is high. 9. H= Goes to level of pullup voltage. 10.B* = Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.

Philips Semiconductors FAST Products Product specification 74F8960/74F8961Octal latched bidirectional Futurebus transceivers (3-State + open-collector) December 19, 1990 6 FUNCTION TABLE FOR 74F8961 INPUTS LATCH OUTPUTS OPERATING MODE An Bn* LE OEA OEB OEB STATE An Bn H X L L L L H Z H A 3–state, data from A to B L X L L L L L Z L X X H L L L Qn Z Qn A 3–state, latched data to B – – L H L L (1) (1) (1) Feedback: A to B, B to A – H H H L L H (2) H Z(2) Preconditioned latch enabling data transfer from B to A – L H H L L H (2) L Z(2) – – H H L L Qn Qn Qn Latch state to A and B H X L L H X H Z Z l X L L H X l Z Z B and A 3–state X X H L H X Qn Z Z – H L H H X H H Z – L L H H H L L Z B 3–state, data from B to A – H H H H H Qn H Z – L H H H H Qn L Z H X L L X H H Z Z l X L L X H l Z Z B and A 3–state X X H L X H Qn Z Z – H L H X H H H Z – L L H X H L L Z B 3–state, data from B to A – H H H X H Qn H Z – L H H X H Qn L Z NOTES: 1. H = High–voltage level 2. L = Low–voltage level 3. X = Don’t care 4. – = Input not externally driven 5. Z = High impedance (off) state 6. Qn = High or low–voltage level one setup time prior to the low–to–high LE transition. 7. (1) =Condition will cause a feedback loop path: A to B and B to A. 8. (2) =The latch must be preconmditioned such that B inputs may assume a high or low level while OEB0 and OEB1 are low and LE is high. 9. H= Goes to level of pullup voltage. 10.B* = Precaution should be taken to insure the B inputs do not float. If they do they are equal to low state.

Philips Semiconductors FAST Products Product specification 74F8960/74F8961Octal latched bidirectional Futurebus transceivers (3-State + open-collector) December 19, 1990 7 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VX Threshold control –0.5 to +7.0 V VIN Input voltage OEB , OEA, LE –0.5 to +7.0 V A0 – A7, B0 – B7 –0.5 to +5.5 V IIN Input current –40 to +5 mA VOUT Voltage applied to output in high output state –0.5 to VCC V IOUT Current applied to output in low output state A0 – A7 48 mA B0 – B7 200 mA Tamb Operating free air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIH High–level input voltage Except B0 – B7 2.0 V B0 – B7 1.6 V VIL Low–level input voltage Except B0 – B7 0.8 V B0 – B7 1.475 V IIk Input clamp current Except A0 – A7 –18 mA A0 – A7 –40 mA IOH High–level output current A0 – A7 –3 mA IOL Low–level output current A0 – A7 24 mA B0 – B7 100 mA Tamb Operating free air temperature range 0 +70 °C

Philips Semiconductors FAST Products Product specification 74F8960/74F8961Octal latched bidirectional Futurebus transceivers (3-State + open-collector) December 19, 1990 8 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST LIMITS UNIT CONDITIONS 1 MIN. TYP. 2 MAX. IOH High–level output current B0 – B7 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA IOFF Power–off output current B0 – B7 VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V 100 µA VCC = MIN, IOH = –3mA, VX =VCC 2.5 VCC V VOH High-level output voltage A0 – A74 VIL = MAX, VIH = MIN IOH = –4mA, VX =3.13V and 3.47V 2.5 V A0 – A74 VCC = MIN, IOL = 20mA, VX = VCC 0.50 V VOL Low-level output voltage B0 – B78 VIL = MAX IOL = 100mA 1.15 V VIH = MIN IOL = 4mA 0.40 V VIK Input clamp voltage A0 – A7 VCC = MIN, II = IIK -0.5 V Except A0 – A7 VCC = MIN, II = IIK -1.2 V II Input current at OEB n, OEA, LE VCC = MAX, VI = 7.0V 100 µA maximum input voltage A0–A7, B0 – B7 VCC = MAX, VI = 5.5V 1 mA IIH High–level input currentOEB n, OEA, LE VCC = MAX, VI = 2.7V 20 µA B0–B7 VCC = MAX, VI = 2.1V, Bn – An = 0V 100 µA IIL Low–level input current OEB n, OEA, LE VCC = MAX, VI = 0.5V –20 µA B0 – B7 VCC = MAX, VI = 0.3V –100 µA IOZH + IIH Off–state output current, high–level current applied A0 – A7 VCC = MAX, VO = 2.7V 70 µA IOZL + IIL Off–state output current, low–level voltage applied A0 – A7 VCC = MAX, VI = 0.5V –70 µA IX High–level control current VCC = MAX, VX = VCC , LE = OEA = OEBn = 2.7V, A0 – A7 = 2.7V, B0 – B7 = 2.0V, –100 100 µA VCC = MAX, VX = 3.13 & 3.47V, LE = OEA = OEB n = A0 – A7 = 2.7V, B0 – B7 = 2.0V, –10 10 µA IOS Short circuit output A0–A7 only ’F8960 74F8960 VCC = MAX, Bn = 1.3V, OEA = 2.0V, OEBn = 2.7V -60 -150 mA current3 only 74F8961 VCC = MAX, Bn = 1.8V, OEA = 2.0V, OEBn = 2.7V ICCH VCC = MAX 65 100 mA ICC Supply current (total) ICCL VCC = MAX, VIL = 0.5V 100 145 mA ICCZ 75 100 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type and function table for operating mode. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Due to test equipment limitations, actual test conditions are for VIH =1.8v and VIL = 1.3V.

Philips Semiconductors FAST Products Product specification 74F8960/74F8961Octal latched bidirectional Futurebus transceivers (3-State + open-collector) December 19, 1990 9 AC ELECTRICAL CHARACTERISTICS FOR 74F8960 A PORT LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50p, RL = 500Ω MIN TYP MAX MIN MAX tPLH tPHL Propagation delay Bn to An Waveform 1, 2 4.5 6.0 6.0 10.0 8.5 13.5 3.5 7.5 9.5 14.5 ns tPZH tPZL Output enable time to high or low, OEA to An Waveform 4 Waveform 5 8.0 8.5 10.5 11.0 13.5 13.5 7.5 8.5 15.0 16.0 ns tPHZ tPLZ Output enable time from high or low, OEA to An Waveform 4 Waveform 5 2.0 2.0 3.5 4.5 6.5 7.0 2.0 2.0 7.0 7.5 ns B PORT LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C D = 50pF, RU = 9Ω C D = 50pF, RL = 9Ω MIN TYP MAX MIN MAX tPLH tPHL Propagation delay An to Bn Waveform 1, 2 3.5 3.5 5.5 5.0 8.0 8.0 2.0 3.0 9.5 9.0 ns tPLH tPHL Propagation delay LE to Bn Waveform 1, 2 3.5 4.0 5.5 6.5 8.5 9.0 2.5 3.0 9.5 10.5 ns tPLH tPHL Output enable/disable time OEB n to Bn Waveform 1, 2 2.5 3.5 4.5 5.5 7.5 8.5 1.5 3.5 8.0 9.0 ns tTLH tTHL Transition time, Bn port 1.3V to 1.7V, 1.7V to 1.3V Test circuit and waveforms 0.5 0.5 2.0 2.0 4.5 4.5 0.5 0.5 5.0 6.0 ns AC SETUP REQUIREMENTS FOR 74F8960 LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX tsu(H) tsu(L) Setup time, high or low An to LE Waveform 3 5.0 3.0 5.0 5.0 ns th(H ) th(L) Hold time, high or low An to LE Waveform 3 0.0 0.0 0.0 0.0 ns tw (L) LE pulse width, low Waveform 3 4.5 5.0 ns

Philips Semiconductors FAST Products Product specification 74F8960/74F8961Octal latched bidirectional Futurebus transceivers (3-State + open-collector) December 19, 1990 10 AC ELECTRICAL CHARACTERISTICS FOR 74F8961 A PORT LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50p, RL = 500Ω MIN TYP MAX MIN MAX tPLH tPHL Propagation delay Bn to An Waveform 1, 2 5.5 4.5 8.0 6.0 12.0 9.0 5.5 4.5 12.0 9.0 ns tPZH tPZL Output enable time to high or low, OEA to An Waveform 4 Waveform 5 8.0 8.5 10.5 11.0 13.5 13.5 7.5 8.0 15.0 15.5 ns tPHZ tPLZ Output enable time from high or low, OEA to An Waveform 4 Waveform 5 2.0 2.0 3.5 4.5 6.0 7.0 1.5 2.0 6.5 7.5 ns B PORT LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C D = 50pF, RU = 9Ω C D = 50pF, RU = 9Ω MIN TYP MAX MIN MAX tPLH tPHL Propagation delay An to Bn Waveform 1, 2 3.0 3.0 5.0 4.5 7.0 7.5 2.5 2.5 8.0 8.5 ns tPLH tPHL Propagation delay LE to Bn Waveform 1, 2 3.5 3.5 5.0 5.0 8.0 8.0 3.0 2.5 9.0 9.0 ns tPLH tPHL Output enable/disable time OEB n to Bn Waveform 1, 2 3.0 3.5 4.5 5.5 7.0 9.0 2.5 3.5 8.0 10.0 ns tTLH tTHL Transition time, Bn port 1.3V to 1.7V, 1.7V to 1.3V Test circuit and waveforms 0.5 0.5 2.0 2.0 4.5 4.5 0.5 0.5 5.0 4.5 ns AC SETUP REQUIREMENTS FOR 74F8961 LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX tsu(H) tsu(L) Setup time, high or low An to LE Waveform 3 3.5 4.5 4.5 5.0 ns th(H ) th(L) Hold time, high or low An to LE Waveform 3 0.0 0.0 0.0 0.0 ns tw (L) LE pulse width, low Waveform 3 4.0 5.0 ns

Philips Semiconductors FAST Products Product specification 74F8960/74F8961Octal latched bidirectional Futurebus transceivers (3-State + open-collector) December 19, 1990 11 AC WAVEFORMS VMVM VMVM Waveform 1. Propagation delay for data to output W aveform 3. Data setup and hold times and LE pulse width W aveform 4. 3–state output enable time to high level and output disable time from high level W aveform 5. 3-state output enable time to low level and output disable time from low level LE VM VM VM VM VM VM ts(L) t s(H) th(L) th(H) VM VM VM tPHZtPZH VOH -0.3V VM VM VM tPLZtPZL VOL +0.3V OEA An OEA An An An, Bn An, Bn, OEBn tPLH tPHL VM tw (L) VMVM VMVM Waveform 2. Propagation delay for data to output An, Bn An, Bn, OEBn tPHL tPLH NOTES: 1. For all waveforms, VM = 1.5V. 2. The shaded areas indicate when the input is permitted to change for predictable output performance. TEST CIRCUITS AND WAVEFORMS C D tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) Low V Low V tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tw tTLH tTHL Input pulse definition VCC family 74F D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test circuit for 3–state outputs on A port DEFINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R U = Pull up resistor; see AC electrical characteristics for value. C D = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = T ermination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude VM R L 7.0V VCC D.U.T.PULSE GENERATOR R T VIN VOUT Test circuit for outputs on B port R U 7.0V Low V SWITCH POSITION TEST SWITCH closed openAll other tPLZ , tPZL