74F841 PHILIPS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 18

Technical content

/C0080 /C0115 /C0111/C0110/C0111 /C0115 74F841/842/843/845/846 Bus interface latches Product specification Replaces datasheet 74F841/842/843/844/845/846 of 1999 Jan 08 IC15 Data Handbook

1999 Jun 23

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches 74F841/74F842 10-bit bus interface latches, non-inverting/inverting (3-State) 74F843 9-bit bus interface latch, non-inverting (3-State) 74F845/74F846 8-bit bus interface latches, non-inverting/inverting (3-State)

21999 Jun 23 853–1208 21851

FEATURES

  • High speed parallel latches
  • Extra data width for wide address/data paths or buses carrying parity
  • High impedance NPN base input structure minimizes bus loading
  • IIL is 20µA vs 1000A for AM29841 series
  • Buffered control inputs to reduce AC effects
  • Ideal where high speed, light loading, or increased fan-in are required as with MOS microprocessors
  • Positive and negative over-shoots are clamped to ground
  • 3-State outputs glitch free during power-up and power-down
  • 48mA sink current
  • Slim dual in-line 300 mil package
  • Broadside pinout
  • Pin-for-pin and function compatible with AMD AM29841-846 series TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74F841, 74F842 5.5ns 60mA 74F843, 74F845 5.5ns 75mA 74F846 6.2ns 60mA

DESCRIPTION

The 74F841–74F846 bus interface latch series are designed to provide extra data width for wider address/data paths of buses carrying parity. The 74F841–74F846 series are funcitonally an pin compatible to the AMD AM29841–AM29846 series. The 74F841 consists of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the LE High-to-Low transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (OE ) is Low. When OE is High the output is in the High-impedance state. The 74F842 is the inverted output version of the 74F841. The 74F843 consists of nine D-type latches with 3-State outputs. In addition to the LE and OE pins, the 74F843 has a Master Reset (MR ) pin and Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance systems. When MR is Low, the outputs are Low if OE is Low. When MR is High, data can be entered into the latch. When PRE is Low, the outputs are High, if OE is Low, PRE overrides MR. The 74F845 consists of eight D-type latches with 3-State outputs. In addition to the LE, OE, MR and PRE pins, the 74F845 has two addtitional OE pins making a total of three Output Enables (OE0, OE 1, OE2) pins. The multiple Ouptut Enables (OE0, OE1, OE2) allow multi-user control of the interface, e.g., CS, DMA, and RD/WR. The 74F846 is the inverted output version of the 74F845.

ORDERING INFORMATION

VCC = 5V±10%; Tamb = 0°C to +70°C PACKAGE DRAWING NUMBER 24-pin plastic Slim DIP (300 mil)N74F841N, N74F842N, N74F843N, N74F845N, N74F846N SOT222-1 24-pin plastic SOL N74F841D, N74F842D, N74F843D, N74F845D, N74F846D SOT137-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dn Data inputs 1.0/0.033 20µA/20µA LE Latch Enable input 1.0/0.033 20µA/20µA OE , OEn Output Enable input (active Low) 1.0/0.033 20µA/20µA MR Master Reset input (active Low) 1.0/0.033 20µA/20µA PRE Preset input (active Low) 1.0/0.033 20µA/20µA Qn Data outputs 1200/80 24mA/48mA Q n Data outputs 1200/80 24mA/48mA NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 3

PIN CONFIGURATION for 74F841 12 13 24OE VCC LEGND SF01279 LOGIC SYMBOL for 74F841 SF01280 3456 789 1 0 LE D1 D2 D3 D4 D5 D6 D7 D8 OE VCC = Pin 24 GND = Pin 12 23 22 21 20 19 18 17 16 15 14 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 LOGIC SYMBOL (IEEE/IEC) for 74F841 232 1 D SF01281 EN 223 1411 PIN CONFIGURATION for 74F842 12 13 24OE VCC Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 7 Q 6 Q 8 Q 9 LEGND SF01282 LOGIC SYMBOL for 74F842 SF01283 3456 789 1 0 LE D1 D2 D3 D4 D5 D6 D7 D8 OE VCC = Pin 24 GND = Pin 12 23 22 21 20 19 18 17 16 15 14 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 LOGIC SYMBOL (IEEE/IEC) for 74F842 232 1 D SF01284 EN 223 1411

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 4

PIN CONFIGURATION for 74F843 12 13 24OE MR VCC PRE LEGND SF01285 LOGIC SYMBOL for 74F843 SF01286 3456 789 1 0 LE D1 D2 D3 D4 D5 D6 D7 D8 VCC = Pin 24 GND = Pin 12 23 22 21 20 19 18 17 16 15 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

14 PRE

LOGIC SYMBOL (IEEE/IEC) for 74F843 232 1 D SF01287 EN R 223

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 5

PIN CONFIGURATION for 74F845 12 13 24OE 0 OE 1 MR VCC OE 2 PRE LEGND SF01291 LOGIC SYMBOL for 74F845 SF01292 3456 789 1 0 LE D1 D2 D3 D4 D5 D6 D7 VCC = Pin 24 GND = Pin 12 22 21 20 19 18 17 16 15 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

1 OE0

2 OE1

23 OE2

LOGIC SYMBOL (IEEE/IEC) for 74F845 223 1 D SF01293A 14 S2 R EN PIN CONFIGURATION for 74F846 12 13 24OE 0 OE 1 MR VCC OE 2 Q 0 Q 1 Q 2 Q 3 Q 4 Q 6 Q 5 Q 7 PRE LEGND SF01294 LOGIC SYMBOL for 74F846 SF01295 3456 789 1 0 LE D1 D2 D3 D4 D5 D6 D7 VCC = Pin 24 GND = Pin 12 22 21 20 19 18 17 16 15 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LOGIC SYMBOL (IEEE/IEC) for 74F846 223 1 D SF01296A 14 S2 R EN

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 6

VCC = Pin 24 GND = Pin 12 LQ D 13LE LQ D LQ D LQ D LQ D LQ D LQ C D LQ D LQ D LQ D SF01297 LOGIC DIAGRAM for 74F842 1OE VCC = Pin 24 GND = Pin 12 LQ D Q 0 13LE LQ D Q 1 LQ D Q 2 LQ D Q 3 LQ D Q 4 LQ D Q 5 LQ C D Q 6 LQ D Q 7 LQ D Q 8 LQ D Q 9 SF01298 FUNCTION TABLE for 74F841 and 74F842 INPUTS OUTPUTS INPUTS 74F841 74F842 OPERATING MODE OE LE Dn Qn Q n L H L L H Transparent L H H H L Transparent L ↓ l L H Latched L ↓ h H L Latched H X X Z Z High Impedance L L X NC NC Hold H = High voltage level L = Low voltage level h = High state one setup time before the High-to-Low LE transition l = Low state one setup time before the High-to-Low LE transition ↓ = High-to-Low transition X = Don’t care NC= No change Z = High impedance “off” state

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 7

VCC = Pin 24 GND = Pin 12 LQ C DP 13LE 11MR 14PRE LQ C DP LQ C DP LQ C DP LQ C DP LQ C DP LQ C DP LQ C DP LQ C DP SF01299 FUNCTION TABLE for 74F843 INPUTS OUTPUTS INPUTS 74F843 OPERATING MODE OE PRE MR LE Dn Qn L L X X X H Preset L H L X X L Clear L H H H L L Transparent L H H H H H Transparent L H H ↓ l L Latched L H H ↓ h H Latched H X X X X Z High Impedance L H H L X NC Hold H = High voltage level L = Low voltage level h = High state one setup time before the High-to-Low LE transition l = Low state one setup time before the High-to-Low LE transition ↓ = High-to-Low transition X = Don’t care NC= No change Z = High impedance “off” state

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 8

VCC = Pin 24 GND = Pin 12 LQ C DP 13LE 11MR 14PRE LQ C DP LQ C DP LQ C DP LQ C DP LQ C DP LQ C DP LQ C DP SF01301 LOGIC DIAGRAM for 74F846 OE OE 1 OE 2 VCC = Pin 24 GND = Pin 12 LQ C DP Q 0 13LE 11MR 14PRE LQ C DP Q 1 LQ C DP Q 2 LQ C DP Q 3 LQ C DP Q 4 LQ C DP Q 5 LQ C DP Q 6 LQ C DP Q 7 SF01302 FUNCTION TABLE for 74F845 and 74F846 INPUTS OUTPUTS INPUTS 74F845 74F846 OPERATING MODE OE PRE MR LE Dn Qn Q n L L X X X H H Preset L H L X X L L Clear L H H H L L H Transparent L H H H H H L Transparent L H H ↓ l L H Latched L H H ↓ h H L Latched H X X X X Z Z High Impedance L H H L X NC NC Hold H = High voltage level L = Low voltage level h = High state one setup time before the High-to-Low LE transition l = Low state one setup time before the High-to-Low LE transition ↓ = High-to-Low transition X = Don’t care NC= No change Z = High impedance “off” state

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 9

Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 84 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNITSYMBOL PARAMETER MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –24 mA IOL Low-level output current 48 mA Tamb Operating free-air temperature range 0 +70 °C

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 10

DC ELECTRICAL CHARACTERISTICS Over recommended operating free-air temperature range unless otherwise noted. SYMBOL PARAMETER TEST CONDITIONS 1 LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS 1 MIN TYP 2 MAX UNIT IO = 15mA ±10%V CC 2.2 V VO High level output voltage VCC = MIN, IOH = –15mA ±5%V CC 2.2 3.3 V VOH High-level output voltage CC , VIL = MAX, VIH = MIN IO = 24mA ±10%V CC 2.0 V IOH = –24mA ±5%V CC 2.0 V VO Low level output voltage VCC = MIN, IOL = 32mA ±10%V CC 0.38 0.55 V VOL Low-level output voltage CC , VIL = MAX, VIH = MIN IOL = 48mA ±5%V CC 0.38 0.55 V VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V II Input current at maximum input voltage VCC = 0.0V, VI = 7.0V 100 µA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –20 µA IOZH Off-state output current, High-level voltage applied VCC = MAX, VO = 2.7V 50 µA IOZL Off-state output current, Low-level voltage applied VCC = MAX, VO = 0.5V –50 µA IOS Short-circuit output current3 VCC = MAX –100 –225 mA ICCH 50 65 mA 74F841 ICCL VCC = MAX 60 80 mA ICCZ 70 92 mA ICCH 40 60 mA 74F842 ICCL VCC = MAX 65 90 mA ICC Supply current ICCZ 60 90 mA ICC y (total) ICCH 65 90 mA 74F843 74F845 ICCL VCC = MAX 75 100 mA74F845 ICCZ 85 115 mA ICCH 50 70 mA 74F846 ICCL VCC = MAX 70 95 mA ICCZ 70 95 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter test, IOS tests should be performed last.

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 11

AC ELECTRICAL CHARACTERISTICS for 74F841/74F842 LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX tPLH tPHL Propagation delay Dn to Qn 74F841 Waveform 1, 2 2.0 2.5 4.0 4.5 7.5 7.5 2.0 2.5 8.0 8.0 ns tPLH tPHL Propagation delay LE to Qn 74F841 Waveform 1, 2 4.5 4.0 6.5 6.0 9.5 9.0 4.0 3.5 10.0 9.5 ns tPLH tPHL Propagation delay Dn to Q n 74F842 Waveform 1, 2 3.5 3.0 5.5 5.0 8.5 8.0 4.5 4.0 9.0 8.5 ns tPLH tPHL Propagation delay LE to Q n 74F842 Waveform 1, 2 5.0 4.5 7.0 6.5 10.0 9.0 3.0 3.0 10.5 9.5 ns tPZH tPZL Output enable time High or Low-level OE n to Qn or Qn Waveform 5 Waveform 6 2.5 4.0 4.5 6.0 8.0 9.5 2.0 3.0 8.5 10.5 ns tPHZ tPLZ Output disable time High or Low-level OE n to Qn or Qn Waveform 5 Waveform 6 1.0 1.0 4.5 5.0 8.0 8.0 1.0 1.0 8.5 8.5 ns AC SETUP REQUIREMENTS for 74F841/74F842 LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MIN MAX ts(H) ts(L) Setup time, High or Low Dn to LE Waveform 4 0.0 0.0 1.0 1.0 ns th(H) th(L) Hold time, High or Low Dn to LE 74F841 Waveform 4 2.5 3.0 3.0 4.0 ns tw (H) LE pulse width, High Waveform 4 3.5 4.0 ns th(H) th(L) Hold time, High or Low Dn to LE 74F842 Waveform 4 3.0 3.5 3.5 4.5 ns tw (H) LE pulse width, High Waveform 4 3.0 3.0 ns

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 12

AC ELECTRICAL CHARACTERISTICS for 74F843/74F845 LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX tPLH tPHL Propagation delay Dn to Qn Waveform 1, 2 2.0 2.5 4.5 4.5 7.5 8.0 2.0 2.5 8.5 8.5 ns tPLH tPHL Propagation delay LE to Qn Waveform 1, 2 4.5 4.0 6.5 6.0 9.5 8.5 4.5 4.0 10.0 8.5 ns tPLH Propagation delay PRE tPHL Propagation delay MR tPZH tPZL Output enable time High or Low-level OE n to Qn Waveform 5 Waveform 6 2.5 4.0 4.5 6.0 7.5 9.5 2.0 3.0 8.0 10.5 ns tPHZ tPLZ Output disable time High or Low-level OE n to Qn Waveform 5 Waveform 6 1.0 1.0 4.5 5.0 8.0 8.0 1.0 1.0 8.5 8.5 ns AC SETUP REQUIREMENTS for 74F843/74F845 LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MIN MAX ts(H) ts(L) Setup time, High or Low Dn to LE Waveform 4 1.0 1.0 0.0 0.0 ns th(H) th(L) Hold time, High or Low Dn to LE Waveform 4 3.0 4.0 3.0 4.0 ns tw (H) LE pulse width, High Waveform 4 3.0 3.0 ns tw (L) PRE pulse width, Low Waveform 3 4.0 5.0 ns tw (H) MR pulse width, Low Waveform 3 4.0 5.0 ns tREC PRE recovery time Waveform 3 0.0 0.0 ns tREC MR recovery time Waveform 3 3.5 4.5 ns

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 13

AC ELECTRICAL CHARACTERISTICS for 74F846 LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX tPLH tPHL Propagation delay Dn to Qn Waveform 1, 2 3.5 3.0 5.5 5.0 8.5 8.0 3.0 3.0 9.5 8.5 ns tPLH tPHL Propagation delay LE to Q n Waveform 1, 2 5.0 4.5 7.0 6.5 10.0 9.0 5.0 4.5 10.5 9.5 ns tPLH Propagation delay PRE tPHL Propagation delay MR tPZH tPZL Output enable time High or Low-level OE n to Qn Waveform 5 Waveform 6 2.5 4.0 5.0 6.0 7.5 9.5 2.0 3.0 8.0 10.5 ns tPHZ tPLZ Output disable time High or Low-level OE n to Qn Waveform 5 Waveform 6 1.0 1.0 4.5 5.0 8.0 8.0 1.0 1.0 8.5 8.5 ns AC SETUP REQUIREMENTS for 74F846 LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MIN MAX ts(H) ts(L) Setup time, High or Low Dn to LE Waveform 4 0.0 0.0 0.0 0.0 ns th(H) th(L) Hold time, High or Low Dn to LE Waveform 4 3.0 4.0 3.0 4.0 ns tw (H) LE pulse width, High Waveform 4 3.0 3.0 ns tw (L) PRE pulse width, Low Waveform 3 4.0 5.0 ns tw (H) MR pulse width, Low Waveform 3 4.0 5.0 ns tREC PRE recovery time Waveform 3 0.0 0.0 ns tREC MR recovery time Waveform 3 3.5 4.5 ns

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 14

For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. VM VM VM VM tPHLtPLH Dn, LE Qn SF01303 Waveform 1. Propagation Delay, Non-Inverting Path VM VM VM VM tPLHtPHL Dn, LE Q n SF01304 Waveform 2. Propagation Delay, Inverting Path LE VMVMPRE , MR VM tw (L) tREC VM VM tPLH tPHL Qn, Qn Qn, Qn SF01305 Waveform 3. Master Reset and Preset Pulse Width, Master Reset and Preset to Output Delay, and Master Reset and Preset to Latch Enable Recovery Time th(H)ts(H) LE VM VM VMVMVM VM th(L)ts(L) Dn VM tw (H) SF01306 Waveform 4. Data Setup and Hold Times VM VM VM tPHZtPZH OE n VOH -0.3V Qn, Qn SF00509 Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level VM VM VM tPLZtPZL VOL +0.3V 3.5V OE n Qn, Qn SF00510 Waveform 6. 3-State Output Enable Time to Low Level and Output Disable time from Low Level

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 15

TEST CIRCUIT AND WAVEFORMS tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns Input Pulse Definition VCC family 74F D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test Circuit for 3-State Outputs DEFINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = Termination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude 3.0V 1.5V VM R L 7.0V SF00777 TEST SWITCH tPLZ closed tPZL closed All other open SWITCH POSITION

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 16

DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 17

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846Bus interface latches

1999 Jun 23 18

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 06-99 Document order number: 9397 750 06143 /C0080 /C0115 /C0111/C0110/C0111 /C0115 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.