74F845 FAIRCHILD | Alldatasheet

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■ 3-STATE outputs ■ Direct replacement for AMD's Am29845 Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F845SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F845SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

www.fairchildsemi.com 2 74F845 Unit Loading/Fan Out Functional Description The 74F845 consists of eight D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation as the output transition follows the data in transi- tion. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the output Enable (OE ) is LOW. When OE is HIGH, the bus output is in the high impedance state. Function Table H = HIGH Voltage Level Z = High Impedance L = LOW Voltage Level NC = No Change X = Immaterial Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL D 0–D 7 Data Inputs 1.0/1.0 20 µA/−0.6 mA O 0–O 7 Data Outputs 150/40 −3.0 µA/24 mA OE 1–OE 3 Output Enables 1.0/1.0 20 µA/−0.6 mA LE Latch Enable 1.0/1.0 20 µA/−0.6 mA CLR Clear 1.0/1.0 20 µA/−0.6 mA PRE Preset 1.0/1.0 20 µA/−0.6 mA Inputs Internal Output Function CLR PRE OE LE D Q O H H H X X X Z High Z H H H H L L Z High Z H H H H H H Z High Z HHHLX N C ZL a t c h e d H H L H L L L Transparent H H L H H H H Transparent H H L L X NC NC Latched H L L X X H H Preset L H L X X L L Clear L L L X X H H Preset L H H L X L Z Latched H L H L X H Z Latched

3 www.fairchildsemi.com 74F845 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.5 I OH = −1 mA Voltage 10% V CC 2.4 VM i n IOH = −3 mA 5% VCC 2.7 I OH = −1 mA 5% VCC 2.7 I OH = −3 mA VOL Output LOW Voltage 10% V CC 0.5 V Min I OL = 24 mA IIH Input HIGH Current 5.0 µAM a x V IN = 2.7V IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V Breakdown Test ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V IOZH Output Leakage Current 50 µAM a x V OUT = 2.7V IOZL Output Leakage Current −50 µAM a x V OUT = 0.5V IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V IZZ Bus Drainage Test 500 µA0 . 0 V V OUT = 5.25V ICCZ Power Supply Current 63 85 mA Max V O = HIGH Z

www.fairchildsemi.com 4 74F845 AC Operating Requirements Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max ns ns tPLH Propagation Delay PRE to On tPHL Propagation Delay CLR to On Symbol Parameter TA = +25°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V Min Max Min Max tS(H) Setup Time, HIGH or LOW 2.0 2.5 ns tS(L) D n to LE 2.0 2.5 tH (H) Hold Time, HIGH or LOW 2.5 3.0 ns tH (L) D n to LE 3.0 3.5 tW (H) LE Pulse Width, HIGH 4.0 4.0 ns tW (L) PRE Pulse Width, LOW 5.0 5.0 ns tW (L) CLR Pulse Width, LOW 5.0 5.0 ns tREC PRE Recovery Time 10.0 10.0 ns tREC CLR Recovery Time 12.0 13.0 ns

5 www.fairchildsemi.com 74F845 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B

www.fairchildsemi.com 6 74F845 8-Bit Transparent Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com