74F827 FAIRCHILD | Alldatasheet

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Ordering Code: Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 74F827 74F828 Order Number Package Number Package Description 74F827SC (Note 1) M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74F827SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 74F828SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74F828SPC (Note 1) N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

www.fairchildsemi.com 2 74F827  74F828 Logic Symbols 74F827 IEEE/IEC 74F827 74F828 IEEE/IEC 74F828 Unit Loading/Fan Out Functional Description The 74F827 and 74F828 are line drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. The devices have 3-STATE outputs controlled by the Output Enable (OE ) pins. The outputs can sink 64 mA and source 15 mA. Input clamp diodes limit high-speed termination effects. Function Table H = HIGH Voltage level L = LOW Voltage Level Z = High Impedance X = Immaterial Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL OE 1, OE2 Output Enable Input 1.0/1.0 20 µA/−0.6 mA D 0–D 7 Data Inputs 1.0/1.0 20 µA/−0.6 mA O 0–O 7 Data Outputs, 3-STATE 600/106.6 (80) −12 mA/64 mA (48 mA) Inputs Outputs OE D n O n Function 74F827 74F828 L H H L Transparent L L L H Transparent H X Z Z High Z

3 www.fairchildsemi.com 74F827  74F828 Logic Diagrams 74F827 74F828 Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

www.fairchildsemi.com 4 74F827  74F828 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs.DC Electrical Characteristics Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.4 VM i n IOH = −3 mA Voltage 10% V CC 2.0 I OH = −15 mA 5% VCC 2.7 I OH = −3 mA VOL Output LOW Voltage 10% V CC 0.55 V Min I OL = 64 mA IIH Input HIGH 5.0 µAM a x V IN = 2.7V Current IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V Breakdown Test ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V IOZH Output Leakage Current 50 µAM a x V OUT = 2.7V IOZL Output Leakage Current −50 µAM a x V OUT = 0.5V IOS Output Short-Circuit Current −100 −225 mA Max V OUT = 0V IZZ Bus Drainage Test 500 µA0 . 0 V V OUT = 5.25V ICCH Power Supply Current (74F827) 30 45 mA Max V O = HIGH ICCL Power Supply Current (74F827) 60 90 mA Max V O = LOW ICCZ Power Supply Current (74F827) 40 60 mA Max V O = HIGH Z ICCH Power Supply Current (74F828) 14 20 mA Max V O = HIGH ICCL Power Supply Current (74F828) 56 85 mA Max V O = LOW ICCZ Power Supply Current (74F828) 35 50 mA Max V O = HIGH Z

5 www.fairchildsemi.com 74F827  74F828 Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF C L = 50 pF Min Typ Max Min Max Min Max ns ns ns ns

www.fairchildsemi.com 6 74F827  74F828 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B

7 www.fairchildsemi.com 74F827  74F828 10-Bit Buffers/Line Drivers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com