74F821 PHILIPS | Alldatasheet

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/C0109 /C0110 /C0114 74F821/822/823/824/825/826 Bus interface registers Product specification 1996 Jan 05 INTEGRATED CIRCUITS IC15 Data Handbook

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

21996 Jan 05 853-1304 16195

74F821 10-bit bus interface register, non-inverting (3-State) 74F822 10-bit bus interface register, inverting (3-State) 74F823 9-bit bus interface register, non-inverting (3-State) 74F824 9-bit bus interface register, inverting (3-State) 74F825 8-bit bus interface register, non-inverting (3-State) 74F826 8-bit bus interface register, inverting (3-State)

FEATURES

  • High speed parallel registers with positive edge-triggered D-type flip-flops
  • High performance bus interface buffering for wide data/address paths or busses carrying parity
  • High impedance PNP base inputs for reduced loading (20µA in high and low states)
  • IIL is 20µA vs 1000µA for AM29821 series
  • Buffered control inputs to reduce AC effects
  • Ideal where high speed, light loading, or increased fan-in as required with MOS microprocessor
  • Positive and negative over-shoots are clamped to ground
  • 3-State outputs glitch free during power-up and power-down
  • Slim Dip 300 mil package
  • Broadside pinout compatible with AMD AM 29821-29826 series
  • Outputs sink 64mA and source 24mA
  • Industrial temperature range available (–40°C to +85°C) for 74F823

DESCRIPTION

The 74F821 series bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of busses carrying parity. The 74F821/74F822 are buffered 10-bit wide versions of the popular 74F374/74F534 functions. The 74F822 is the inverted output version of 74F821. The 74F823 and 74F824 are 9-bit wide buffered registers with clock enable (CE ) and master reset (MR) which are ideal for parity bus interfacing in high microprogrammed systems. The 74F824 is the inverted version of 74F823. The 74F825 and 74F826 are 8-bit buffered registers with all the 74F823/74F824 controls plus output enable (OE0, OE1, OE2) to allow multiuser control of the interface, e.g., CS, DMA, and RD/WR. They are ideal for uses as an output port requiring high IOL /IOH . The 74F826 is the inverted version of 74F825. TYPE TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL) 74F821, 74F822 180MHz 75mA 74F823, 74F824 180MHz 70mA 74F825, 74F826 180MHz 65mA

ORDERING INFORMATION

DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C PKG. DWG. # 24-pin plastic slim DIP (300mil)N74F821N, N74F822N, N74F823N, N74F824N, N74F825N, N74F826N I74F823N SOT222-1 24-pin plastic SOL N74F821D, N74F822D, N74F823D, N74F824D, N74F825D, N74F826D I74F823D SOT137-1

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 3

INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dn Data inputs 1.0/1.0 20µA/0.6mA 74F821 CP Clock input 1.0/1.0 20µA/0.6mA 74F822 OE Output enable input (active low) 1.0/3.0 20µA/1.8mA Qn, Qn Data outputs 1200/106.7 24mA/64mA Dn Data inputs 1.0/1.0 20µA/0.6mA CP Clock input 1.0/1.0 20µA/0.6mA 74F823 CE Clock enable input (active low) 1.0/3.0 20µA/1.8mA 74F824 MR Master reset input (active low) 1.0/3.0 20µA/1.8mA OE Output enable input (active low) 1.0/3.0 20µA/1.8mA Qn, Qn Data outputs 1200/106.7 24mA/64mA Dn Data inputs 1.0/1.0 20µA/0.6mA CP Clock input 1.0/1.0 20µA/0.6mA 74F825 CE Clock enable input (active low) 1.0/3.0 20µA/1.8mA 74F826 MR Master reset input (active low) 1.0/3.0 20µA/1.8mA OE Output enable input (active low) 1.0/3.0 20µA/1.8mA Qn, Qn Data outputs 1200/106.7 24mA/64mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. PIN CONFIGURATION – 74F821 1312 GND OE CP VCC SF00482 LOGIC SYMBOL – 74F821 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 23456789 23 22 21 20 19 18 17 16 VCC = Pin 24 GND = Pin 12 D8 D9 10 11 Q8 Q9 15 14 SF00483

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 4

IEC/IEEE SYMBOL – 74F821 EN1 2D 23 SF00484 PIN CONFIGURATION – 74F822 1312 GND OE C P Q 0 Q 3 Q 4 Q 5 Q 6 VCC Q 7 Q 1 Q 2 Q 8 Q 9 SF00485 LOGIC SYMBOL – 74F822 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 23456789 23 22 21 20 19 18 17 16 VCC = Pin 24 GND = Pin 12 D8 D9 10 11 Q8 Q9 15 14 SF00486 IEC/IEEE SYMBOL – 74F822 EN1 2D 23 SF00487 PIN CONFIGURATION – 74F823 1312 GND OE CP VCC CE MR SF00488 LOGIC SYMBOL – 74F823 CP CE MR OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 23 456789 23 22 21 20 19 18 17 16 V CC = Pin 24 GND = Pin 12 SF00489

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 5

IEC/IEEE SYMBOL – 74F823 1G2 2D 23 EN1 R SF00490 PIN CONFIGURATION – 74F824 1312 GND OE CP Q 0 Q 3 Q 4 Q 5 Q 6 VCC Q 7 Q 1 Q 2 Q 8 CE MR SF00491 LOGIC SYMBOL – 74F824 CP CE MR OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 23 456789 23 22 21 20 19 18 17 16 V CC = Pin 24 GND = Pin 12 SF00492 IEC/IEEE SYMBOL – 74F824 1G2 2D 23 EN1 R SF00493 PIN CONFIGURATION – 74F825 1312

1 VCC

LOGIC SYMBOL – 74F825 CP CE MR OE0 OE1 OE2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 3 456789 22 21 20 19 18 17 16V CC = Pin 24 GND = Pin 12 SF00495

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 6

IEC/IEEE SYMBOL – 74F825 1G2 2D 22 R EN SF00496 PIN CONFIGURATION – 74F826 1312

1 VCCOE 0

LOGIC SYMBOL – 74F826 CP CE MR OE0 OE1 OE2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 3 456789 22 21 20 19 18 17 16 V CC = Pin 24 GND = Pin 12 SF00498 IEC/IEEE SYMBOL – 74F826 1G2 2D 22 R EN SF00499 LOGIC DIAGRAM FOR 74F821 VCC = Pin 24 GND = Pin 12 D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q CP OE SF00500

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 7

VCC = Pin 24 GND = Pin 12 D CP Q Q 0 D CP Q Q 1 D CP Q Q 2 D CP Q Q 3 D CP Q Q 4 D CP Q Q 5 D CP Q Q 6 D CP Q Q 7 D CP Q Q 8 D CP Q Q 9 13CP SF00501 1OE FUNCTION TABLE FOR 74F821 AND 74F822 INPUTS OUTPUTS INPUTS 74F821 74F822 OPERATING MODE OE CP Dn Q Q L ↑ l L H Load and read data L ↑ h H L Load and read data L ↑ X NC NC Hold H X X Z Z High impedance H = High-voltage level h = High state must be present one setup time before the low-to-high clock transition L = Low-voltage level l = Low state must be present one setup time before the low-to-high clock transition NC= No change X = Don’t care Z = High impedance “off” state ↑ = Low-to-high clock transition = Not low-to-high clock transition LOGIC DIAGRAM FOR 74F823 VCC = Pin 24 GND = Pin 12 D R Q 11MR CP CE SF00502A CP 13 OE D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 8

VCC = Pin 24 GND = Pin 12 D R Q Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 11MR CP CE SF00503A OE CP D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP FUNCTION TABLE for 74F823 and 74F824 INPUTS OUTPUTS INPUTS 74F823 74F824 OPERATING MODE OE MR CE * CP Dn Q Q L L X X X L L Clear L H L ↑ h H L Load and read data L H L ↑ l L H Load and read data L H H X X NC NC Hold H X X X X Z Z High impedance H = High-voltage level h = High state must be present one setup time before the low-to-high clock transition L = Low-voltage level l = Low state must be present one setup time before the low-to-high clock transition NC= No change X = Don’t care Z = High impedance “off” state * = Since CE input is sensitive to very short (<3ns) high-to-low-to-high going spikes while CP is high, users should avoid the use of decoders or other potentially glitch prone device on the CE input. ↑ = Low-to-high clock transition LOGIC DIAGRAM FOR 74F825 VCC = Pin 24 GND = Pin 12 D R Q 11MR CP CE OE 0 SF00504A 13CP 2OE 1 OE 2 D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 9

VCC = Pin 24 GND = Pin 12 D R Q Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 CP CE 14 11MR OE 0 SF00505A CP OE 1 OE 2 D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP D R Q CP FUNCTION TABLE FOR 74F825 AND 74F826 INPUTS OUTPUTS INPUTS 74F825 74F826 OPERATING MODE OE n MR CE * CP Dn Q Q L L X X X L L Clear L H L ↑ h H L Load and read data L H L ↑ l L H Load and read data L H H X X NC NC Hold H X X X X Z Z High impedance H = High-voltage level h = High state must be present one setup time before the low-to-high clock transition L = Low-voltage level l = Low state must be present one setup time before the low-to-high clock transition NC= No change X = Don’t care Z = High impedance “off” state * = Since CE input is sensitive to very short (<3ns) high-to-low-to-high going spikes while CP is high, users should avoid the use of decoders or other potentially glitch prone device on the CE input. ↑ = Low-to-high clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in high output state –0.5 to VCC V IOUT Current applied to output in low output state 128 mA T O perating free air temperature range Commercial range 0 to +70 °C Tamb Operating free-air temperature range Industrial range –40 to +85 °C Tstg Storage temperature range –65 to +150 °C

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 10

RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNITSYMBOL MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIk Input clamp current –18 mA IOH High–level output current –24 mA IOL Low–level output current 64 mA T b O perating free-air temperature range Commercial range 0 +70 °C Tamb O erating free-air tem erature range Industrial range –40 +85 °C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS 1 LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS 1 MIN TYP 2 MAX UNIT IO = 15mA ±10%V CC 2.4 V VO High level output voltage VCC = MIN, VIL= MAX IOH = –15mA ±5%V CC 2.4 V VOH High-level output voltage VIL = MAX , VIH = MIN IO = 24mA ±10%V CC 2.0 V IOH = –24mA ±5%V CC 2.0 V VO Low level output voltage VCC = MIN, VIL= MAX IO = MAX ±10%V CC 0.55 V VOL Low-level output voltage VIL = MAX , VIH = MIN IOL = MAX ±5%V CC 0.42 0.55 V VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V II Input current at maximum input voltage VCC = 0.0V, VI = 7.0V 100 µA IIH High–level input current VCC = MAX, VI = 2.7V 20 µA IIL Low–level input current VCC = MAX, VI = 0.5V –20 µA IOZH Off–state output current, high–level voltage appliedVCC = MAX, VO = 2.7V 50 µA IOZL Off–state output current, low–level voltage appliedVCC = MAX, VO = 0.5V –50 µA IOS Short–circuit output current3 VCC = MAX -100 -225 mA ICCH 75 105 mA 74F821, 74F822 ICCL VCC = MAX 75 105 mA74F822 ICCZ 75 115 mA ICCH 65 100 mA ICC Supply current (total) 74F823, 74F824 ICCL VCC = MAX 70 105 mA74F824 ICCZ 75 110 mA ICCH 60 85 mA 74F825, 74F826 ICCL VCC = MAX 60 90 mA74F826 ICCZ 65 95 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 11

AC ELECTRICAL CHARACTERISTICS FOR 74F821/74F822/74F824/74F825/74F826 LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C VCC = +5.0V C L = 50pF, RL = 500Ω Tamb = 0°C to +70°C VCC = +5.0V ± 10% C L = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX fmax Maximum clock frequency Waveform 1 150 180 140 ns tPLH tPHL Propagation delay CP to Qn or Qn 74F821, 74F825, 74F826 Waveform 1 4.0 4.0 6.5 6.0 8.5 8.5 4.0 3.5 9.5 9.0 ns tPLH tPHL Propagation delay CP to Q n 74F822, 74F824 Waveform 1 4.5 4.5 6.5 6.5 9.0 9.0 4.5 4.5 10.0 9.0 ns tPHL Propagation delay MR to Qn or Qn 74F824 tPZH tPZL Output enable time OE n to Qn or Qn Waveform 4 Waveform 5 2.0 3.0 4.5 5.0 8.0 8.0 2.0 2.5 9.0 9.0 ns tPHZ tPLZ Output disable time OE n to Qn or Qn Waveform 4 Waveform 5 1.5 1.5 3.5 3.5 6.5 6.5 1.5 1.5 7.5 7.5 ns AC SETUP REQUIREMENTS FOR 74F821/74F822/74F824/74F825/74F826 LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C VCC = +5.0V C L = 50pF, RL = 500Ω Tamb = 0°C to +70°C VCC = +5.0V ± 10% C L = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX tsu (H) tsu (L) Setup time, high or low Dn to CP Waveform 3 1.0 1.0 1.0 1.0 ns th (H) th (L) Hold time, high or low Dn to CP Waveform 3 2.0 2.0 2.0 2.0 ns tw (H) tw (L) CP Pulse width, high or low Waveform 1 3.5 3.5 4.0 4.0 ns tsu (H) tsu (L) Setup time, high or low, CE to CP Waveform 3 0.0 2.0 0.0 2.0 ns th (H) th (L) Hold time, high or low CE to CP 74F824, 74F825, 74F826 Waveform 3 0.0 3.0 0.0 3.5 ns tw (L) MR Pulse width, low 74F826 Waveform 2 4.5 4.5 ns trec Recovery time, MR to CP Waveform 2 2.5 2.5 ns

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 12

AC ELECTRICAL CHARACTERISTICS FOR 74F823 LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C VCC = +5.0V C L = 50pF R L = 500Ω Tamb = 0°C to +70°C VCC = +5.0V ± 10% C L = 50pF R L = 500Ω Tamb = –40°C to +85°C VCC = +5.0V ± 10% C L = 50pF R L = 500Ω UNIT MIN TYP MAX MIN MAX MIN MAX fmax Maximum clock frequency Waveform 1 150 180 140 130 ns tPLH tPHL Propagation delay CP to Qn or Qn Waveform 1 4.0 4.0 6.5 6.0 8.5 8.5 4.0 3.5 9.5 9.0 4.0 3.5 10.0 9.0 ns tPHL Propagation delay MR tPZH tPZL Output enable time OE n to Qn or Qn Waveform 4 Waveform 5 2.0 3.0 4.5 5.0 8.0 8.0 2.0 2.5 9.0 9.0 2.0 2.5 11.0 9.0 ns tPHZ tPLZ Output disable time OE n to Qn or Qn Waveform 4 Waveform 5 1.5 1.5 3.5 3.5 6.5 6.5 1.5 1.5 7.5 7.5 1.5 1.5 8.5 8.5 ns AC SETUP REQUIREMENTS FOR 74F823 LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C VCC = +5.0V C L = 50pF R L = 500Ω Tamb = 0°C to +70°C VCC = +5.0V ± 10% C L = 50pF R L = 500Ω Tamb = –40°C to +85°C VCC = +5.0V ± 10% C L = 50pF R L = 500Ω UNIT MIN TYP MAX MIN MAX MIN MAX tsu (H) tsu (L) Setup time, high or low Dn to CP Waveform 3 1.0 1.0 1.0 1.0 2.0 1.5 ns th (H) th (L) Hold time, high or low Dn to CP Waveform 3 2.0 2.0 2.0 2.0 2.5 2.0 ns tw (H) tw (L) CP Pulse width, high or low Waveform 1 3.5 3.5 4.0 4.0 4.0 4.0 ns tsu (H) tsu (L) Setup time, high or low, CE to CP Waveform 3 0.0 2.0 0.0 2.0 0.0 2.0 ns th (H) th (L) Hold time, high or low CE to CP Waveform 3 0.0 3.0 0.0 3.5 1.5 4.0 ns tw (L) MR Pulse width, low Waveform 2 4.5 4.5 4.5 ns trec Recovery time, MR to CP Waveform 2 2.5 2.5 2.5 ns

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 13

For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. tPHL CP VM VMVM tw (H) 1/fmax VMVM tPHLtw (L)tPLH Qn VMVMQ n tPLH SF00506 Waveform 1. Propagation delay for clock input to output, clock pulse width, and maximum clock frequency VM VM VM trec tPHL MR CP Qn, Qn VM tw (L) SF00507 Waveform 2. Master reset pulse width, master reset to output delay and master reset to clock recovery time VM VM VM VM VM VM tsu(L) t h(L)tsu(H) t h(H) Dn, CE CP SF00508 Waveform 3. Data setup time and hold times VM VM VM tPHZtPZH OE n VOH -0.3V Qn, Qn SF00509 Waveform 4. 3-State output enable time to high level and output disable time from high level VM VM VM tPLZtPZL VOL +0.3V 3.5V OE n Qn, Qn SF00510 Waveform 5. 3-State output enable time to low level and output disable time from low level

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 14

TEST CIRCUIT AND WAVEFORMS tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns Input Pulse Definition VCC family 74F D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test Circuit for Open Collector Outputs DEFINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = Termination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude 3.0V 1.5V VM R L 7.0V SF00128 TEST SWITCH tPLZ closed tPZL closed All other open SWITCH POSITION

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 15

DIP24: plastic dual in-line package; 24 leads (300 mil) SOT222-1

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 16

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers

1996 Jan 05 17

Philips Semiconductors Product specification 74F821/822/823/824/825/826Bus interface registers Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act.  Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Date of release: July 1994 Document order number: 9397-750-05185