74F825 FAIRCHILD | Alldatasheet

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■ 3-STATE output ■ Clock enable and clear ■ Multiple output enables Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F825SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F825SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

www.fairchildsemi.com 2 74F825 Unit Loading/Fan Out Functional Description The 74F825 consists of eight D-type edge-triggered flip- flops. This device has 3-STATE true outputs and is orga- nized in broadside pinning. In addition to the clock and out- put enable pins, the buffered clock (CP) and buffered Output Enable (OE ) are common to all flip-flops. The flip- flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW- to-HIGH CP transition. With the OE LOW the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Opera- tion of the OE input does not affect the state of the flip- flops. The 74F825 has Clear (CLR) and Clock Enable (EN) pins. When the CLR is LOW and the OE is LOW the outputs are LOW. When CLR is HIGH, data can be entered into the flip- flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH the outputs do not change state, regard- less of the data or clock input transitions. Function Table L = LOW Voltage Level Z = High Impedance H = HIGH Voltage Level /c17 = LOW-to-HIGH Transition X = Immaterial NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL D 0–D 7 Data Inputs 1.0/1.0 20 µA/−0.6 mA O 0–O 7 3-STATE Data Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) OE 1, OE2, OE3 Output Enable Input 1.0/1.0 20 µA/−0.6 mA EN Clock Enable 1.0/1.0 20 µA/−0.6 mA CLR Clear 1.0/1.0 20 µA/−0.6 mA CP Clock Input 1.0/2.0 20 µA/−1.2 mA Inputs Internal Output Function OE CLR EN CP D Q O HHL H XN C Z H o l d HHL L XN C Z H o l d H H H X X NC Z Hold LH H X XN C N C H o l d H L X X X H Z Clear L L X X X H L Clear HHL /c17 L H Z Load HHL /c17 H L Z Load LHL /c17 L H L Data Available LHL /c17 H L H Data Available L H L H X NC NC No Change in Data L H L L X NC NC No Change in Data

3 www.fairchildsemi.com 74F825 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.5 VM i n IOH = −1 mA Voltage 10% V CC 2.4 I OH = −3 mA 5% VCC 2.7 I OH = −1 mA 5% VCC 2.7 I OH = −3 mA VOL Output LOW 10% V CC 0.5 V Min I OL = 24 mA Voltage IIH Input HIGH 5.0 µAM a x V IN = 2.7V Current IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V Breakdown Test ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V IOZH Output Leakage Current 50 µAM a x V OUT = 2.7V IOZL Output Leakage Current −50 µAM a x V OUT = 0.5V IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V IZZ Buss Drainage Test 500 µA0 . 0 V V OUT = 5.25V ICCZ Power Supply Current 75 90 mA Max V O = HIGH Z

www.fairchildsemi.com 4 74F825 AC Operating Requirements Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF C L = 50 pF Min Typ Max Min Max Min Max fMAX Maximum Clock Frequency 100 160 60 70 MHz ns tPHL Propagation Delay CLR to On ns Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V V CC = +5.0V Min Max Min Max Min Max tS(H) Setup Time, HIGH or LOW 2.5 4.0 3.0 tS(L) D n to CP 2.5 4.0 3.0 ns tH (H) Hold Time, HIGH or LOW 2.5 2.5 2.5 tH (L) D n to CP 2.5 2.5 2.5 tS(H) Setup Time, HIGH or LOW 4.5 5.0 5.0 tS(L) EN to CP 2.5 3.0 3.0 ns tH (H) Hold Time, HIGH or LOW 2.0 3.0 1.0 tH (L) EN to CP 02 . 00 tW (H) CP Pulse Width 5.0 6.0 6.0 ns tW (L) HIGH or LOW 5.0 6.0 6.0 tW (L) CLR Pulse Width, LOW 5.0 5.0 5.0 ns tREC CLR Recovery Time 5.0 5.0 5.0 ns

5 www.fairchildsemi.com 74F825 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B

www.fairchildsemi.com 6 74F825 8-Bit D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com