74F779 FAIRCHILD | Alldatasheet
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■ Multiplexed 3-STATE I/O ports ■ Built-in lookahead carry capability ■ Count frequency 100 MHz typ ■ Supply current 80 mA typ ■ Available in SOIC (300 mil only) Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Order Number Package Number Package Description 74F779SC M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F779PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com 2 74F779 Unit Loading/Fan Out Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial /c17 = LOW-to-HIGH Clock Transition (Not LL) means S0 and S1 should never both be LOW level at the same time. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL I/O0–I/O7 Data Inputs 0.25/0.33 5 µA/−0.2 mA Data Outputs 75/15 (12.5) −3 mA/24 mA (20 mA) S0, S1 Select Inputs 0.25/0.33 5 µA/−0.2 mA OE Output Enable Input (Active LOW) 0.25/0.33 5 µA/−0.2 mA CET Count Enable Trickle Input (Active LOW) 0.25/0.33 5 µA/−0.2 mA CP Clock Pulse Input (Active Rising Edge) 0.25/0.33 5 µA/−0.2 mA TC Terminal Count Output (Active LOW) 25/12.5 −1 mA/20 mA S1 S0 CET OE CP Function XXXHX I / O 0 to I/O7 in High Z X X X L X Flip-Flop Outputs Appear on I/O Lines LLX H /c17 Parallel Load All Flip-Flops (Not LL) H X /c17 Hold (TC Held HIGH) HLLX /c17 Count Up LHLX /c17 Count Down
3 www.fairchildsemi.com 74F779 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com 4 74F779 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current ((Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.4 VM i n I OH = −3 mA Voltage 5% V CC 2.7 VOL Output LOW 10% V CC 0.5 VM i n IOL = 20 mA Voltage 5% V CC 0.5 I OL = 20 mA IIH Input HIGH Current 5.0 µAM a x V IN = 2.7V (Non-I/O Pins) IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V (Non-I/O Pins) Breakdown Test IBVIT Input HIGH Current 0.5 mA Max V IN = 5.5V (I/On) Breakdown (I/O) ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All other pins grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All other pins grounded IZZ Bus Drainage Test 500 µA0 . 0 V OUT = 5.25V IIL Input LOW Current −0.2 mA Max V IN = 0.5V (Non I/O Pins) IIH + IOZH Output Leakage Current 70 µAM a x V OUT = 2.7V (I/On) IIL + IOZL Output Leakage Current −200 µAM a x V OUT = 0.5V (I/On) IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V ICCH Power Supply Current 90 mA Max V O = HIGH ICCL Power Supply Current 105 mA Max V O = LOW ICCZ Power Supply Current 110 mA Max V O = HIGH Z
5 www.fairchildsemi.com 74F779 AC Operating Requirements Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max fMAX Maximum Clock Frequency 100 105 90 ns Symbol Parameter TA = +25°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V M i nM a xM i nM a x tS(H) Setup Time 5.0 5.0 ns tS(L) I/O n to CP 5.0 5.0 tH (H) Hold Time 0.0 0.0 ns tH (L) I/O n to CP 0.0 0.0 tS(H) Setup Time 9.5 10.0 ns tS(L) S n to CP 9.5 10.0 tH (H) Hold Time 0.0 0.0 ns tH (L) S n to CP 0.0 0.0 tS(H) Setup Time 7.0 7.0 nstS(L) CET to CP 7.0 7.0 tH (H) Hold Time 0.0 0.0 nstH (L) CET to CP 0.0 0.0 tW (H) Clock Pulse Width 4.0 4.0 ns tW (L) HIGH or LOW 4.0 4.0
www.fairchildsemi.com 6 74F779 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M16B
7 www.fairchildsemi.com 74F779 8-Bit Bidirectional Binary Counter with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com