54F676DM NSC | Alldatasheet
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Y 16-bit parallel-to-serial conversion Y 16-bit serial-in, serial-out Y Chip select control Y Slim 24 lead 300 mil package Commercial Military Package Package DescriptionNumber 74F676PC N24A 24-Lead (0.600 × Wide) Molded Dual-In-Line 74F676SPC N24C 24-Lead (0.300 × Wide) Molded Dual-In-Line 54F676DM (Note 2) J24A 24-Lead (0.600 × Wide) Ceramic Dual-In-Line 54F676SDM (Note 2) J24F 24-Lead (0.300 × Wide) Ceramic Dual-In-Line 74F676SC (Note 1) M24B 24-Lead (0.300 × Wide) Molded Small Outline, JEDEC 54F676FM (Note 2) W24C 24-Lead Cerpack 54F676LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13 × reel. Use suffix e SCX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak TL/F/9588–2 Pin Assignment for LCC TL/F/9588–3 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
TL/F/9588–1 IEEE/IEC TL/F/9588–4 Unit Loading/Fan Out 54F/74F Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH/IOL P0 –P15 Parallel Data Inputs 1.0/1.0 20 mA/b0.6 mA CS Chip Select Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA CP Clock Pulse Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA M Mode Select Input 1.0/1.0 20 mA/b0.6 mA SI Serial Data Input 1.0/1.0 20 mA/b0.6 mA SO Serial Output 50/33.3 b1 mA/20 mA Functional Description The 16-bit shift register operates in one of three modes, as indicated in the Shift Register Operations Table. HOLDÐa HIGH signal on the Chip Select (CS ) input pre- vents clocking, and data is stored in the sixteen registers. Shift/Serial LoadÐ data present on the SI pin shifts into the register on the falling edge of CP . Data enters the Q 0 position and shifts toward Q 15 on successive clocks, finally appearing on the SO pin. Parallel LoadÐ data present on P 0 –P15 are entered into the register on the falling edge of CP . The SO output repre- sents the Q 15 register output. To prevent false clocking, CP must be LOW during a LOW- to-HIGH transition of CS . Shift Register Operations Table Control Input Operating Mode CS MC P H X X Hold LL K Shift/Serial Load LH K Parallel Load H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial K e HIGH-to-LOW Transition Block Diagram TL/F/9588–5
Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C Ambient Temperature under Bias b55§Ct o a125§C Junction Temperature under Bias b55§Ct o a175§C Plastic b55§Ct o a150§C VCC Pin Potential to Ground Pin b0.5V to a7.0V Input Voltage (Note 2) b0.5V to a7.0V Input Current (Note 2) b30 mA to a5.0 mA Voltage Applied to Output in HIGH State (with V CC e 0V) Standard Output b0.5V to V CC TRI-STATEÉ Output b0.5V to a5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions Free Air Ambient Temperature Military b55§Ct o a125§C Commercial 0 §Ct o a70§C Supply Voltage Military a4.5V to a5.5V Commercial a4.5V to a5.5V Symbol Parameter 54F/74F Units V CC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage b1.2 V Min I IN eb 18 mA VOH Output HIGH 54F 10% V CC 2.5 I OH eb 1m A Voltage 74F 10% V CC 2.5 V Min I OH eb 1m A 74F 5% V CC 2.7 I OH eb 1m A VOL Output LOW 54F 10% V CC 0.5 V Min IOL e 20 mA Voltage 74F 10% V CC 0.5 I OL e 20 mA IIH Input HIGH 54F 20.0 mA Max VIN e 2.7V Current 74F 5.0 IBVI Input HIGH Current 54F 100 mA Max VIN e 7.0V Breakdown Test 74F 7.0 ICEX Output HIGH 54F 250 mA Max VOUT e VCC Leakage Current 74F 50 VID Input Leakage 74F 4.75 V 0.0 IID e 1.9 mA, Test All Other Pins Grounded IOD Output Leakage 74F 3.75 mA 0.0 VIOD e 150 mV, Circuit Current All Other Pins Grounded IIL Input LOW Current b0.6 mA Max V IN e 0.5V IOS Output Short-Circuit Current b60 b150 mA Max V OUT e 0V ICC Power Supply Current 72 mA Max
TA ea 25§C TA,V CC e Mil T A,V CC e ComSymbol Parameter V CC ea 5.0V CL e 50 pF C L e 50 pF Units CL e 50 pF Min Typ Max Min Max Min Max fmax Maximum Clock Frequency 100 110 45 90 MHz AC Operating Requirements 74F 54F 74F Symbol Parameter TA ea 25§C TA,V CC e Mil T A,V CC e Com UnitsVCC ea 5.0V Min Max Min Max Min Max ts(H) Setup Time, HIGH or LOW 4.0 4.0 4.0 ts(L) SI to CP 4.0 4.0 4.0 ns th(H) Hold Time, HIGH or LOW 4.0 4.0 4.0 th(L) SI to CP 4.0 4.0 4.0 ts(H) Setup Time, HIGH or LOW 3.0 3.0 3.0 ts(L) P n to CP 3.0 3.0 3.0 ns th(H) Hold Time, HIGH or LOW 4.0 4.0 4.0 th(L) P n to CP 4.0 4.0 4.0 ts(H) Setup Time, HIGH or LOW 8.0 8.0 8.0 ts( L ) Mt oC P 8.0 8.0 8.0 ns th(H) Hold Time, HIGH or LOW 2.0 2.0 2.0 th( L ) Mt oC P 2.0 2.0 2.0 ts(L) Setup Time, LOW 10.0 12.0 10.0CS to CP ns th(H) Hold Time, HIGH 10.0 10.0 10.0CS to CP
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 676 S C X Temperature Range Family Special Variations 74FeCommercial QB e Military grade device with 54FeMilitary environmental and burn-in processingDevice Type Temperature RangePackage Code CeCommercial (0 §Ct o a70§C)P e Plastic DIP MeMilitary ( b55§Ct o a125§C)SP e Slim Plastic DIP D e Ceramic DIP SD e Slim Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC
Physical Dimensions inches (millimeters) 28-Lead Ceramic Leadless Chip Carrier (L) 24-Lead Ceramic Dual-In-Line Package (D)
Physical Dimensions inches (millimeters) (Continued) 24-Lead (0.300 × Wide) Ceramic Dual-In-Line Package (SD) 24-Lead (0.300 × Wide) Molded Small Outline Package, JEDEC
Physical Dimensions inches (millimeters) (Continued) 24-Lead (0.600 × Wide) Molded Dual-In-Line Package (P) 24-Lead (0.300 × Wide) Molded Dual-In-Line Package (SP)
54F/74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register Physical Dimensions inches (millimeters) (Continued)
24 Lead Ceramic Flatpak (F)
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