74F673A FAIRCHILD | Alldatasheet

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■ Serial-to-parallel converter ■ 16-bit serial I/O shift register ■ 16-bit parallel-out storage register ■ Recirculating serial shifting ■ Recirculating parallel transfer ■ Common serial data I/O pin ■ Slim 24 lead package Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F673ASC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F673APC N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide 74F673ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

www.fairchildsemi.com 2 74F673A Unit Loading/Fan Out Functional Description The 16-bit shift register operates in one of four modes, as indicated in the Shift Register Operations Table. A HIGH signal on the Chip Select (CS ) input prevents clocking and forces the Serial Input/Output (SI/O) 3-STATE buffer into the high impedance state. During serial shift-out opera- tions, the SI/O buffer is active (i.e., enabled) and the output data is also recirculated back into the shift register. When parallel loading the shift register from the storage register, serial shifting is inhibited. The storage register has an asynchronous master reset (STMR ) input that overrides all other inputs and forces the Q 0–Q 15 outputs LOW. The storage register is in the Hold mode when either CS or the Read/Write (R/W) input is HIGH. With CS and R/W both LOW, the storage register is parallel loaded from the shift register. Shift Register Operations Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial /c16 = HIGH-to-LOW Transition Storage Register Operations Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial /c17 = LOW-to-HIGH Transition Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL CS Chip Select Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA SHCP Shift Clock Pulse Input (Active Falling Edge) 1.0/1.0 20 µA/−0.6 mA STMR Store Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA STCP Store Clock Pulse Input 1.0/1.0 20 µA/−0.6 mA R/W Read/Write Input 1.0/1.0 20 µA/−0.6 mA SI/O Serial Data Input or 3.5/1.0 70 µA/−0.6 mA 3-STATE Serial Output 150/40 −3 mA/24 mA Q 0–Q 15 Parallel Data Outputs 50/33.3 −1 mA/20 mA Control Inputs SI/O Operating Mode CS R/W SHCP STCP Status H X X X High Z Hold L L X Data In Serial Load LH /c16 L Data Out Serial Output with Recirculation LH /c16 H Active Parallel Load; No Shifting Control Inputs Operating STMR CS R/W STCP Mode L X X X Reset; Outputs LOW H H X X Hold HXHX H o l d HLL /c17 Parallel Load

3 www.fairchildsemi.com 74F673A Block Diagram

www.fairchildsemi.com 4 74F673A Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA (Non I/O pins) VOH Output HIGH 10% V CC 2.5 VM i n IOH = −1 mA (Qn, SI/O) Voltage 10% V CC 2.4 I OH = −3 mA (SI/O) 5% VCC 2.7 I OH = −1 mA (Qn, SI/O) 5% VCC 2.7 I OH = −3 mA (SI/O) VOL Output LOW 10% V CC 0.5 VM i n IOL = 20 mA (Qn) Voltage 10% V CC 0.5 I OL = 24 mA (SI/O) IIH Input HIGH Current 20 µAM a x V IN = 2.7V (Non I/O pins) IBVI Input HIGH Current 100 µAM a x V IN = 7.0V (Non I/O pins) Breakdown Test IBVIT Input HIGH Current 1.0 mA Max V IN = 5.5V (SI/O) Breakdown Test (I/O) IIL Input LOW Current −0.6 mA Max V IN = 0.5V IIH + Output Leakage 70 µAM a x V OUT = 2.7V (SI/O) IOZH Current IIL + Output Leakage −650 µAM a x V OUT = 0.5V (SI/O) IOZL Current IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V ICEX Output HIGH Leakage Current 250 µAM a x V OUT = VCC IZZ Bus Drainage Test 500 µA0 . 0 V V OUT = 5.25V ICCH Power Supply Current 114 172 mA Max V O = HIGH ICCL Power Supply Current 114 172 mA Max V O = LOW

5 www.fairchildsemi.com 74F673A AC Operating Requirements Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max fMAX Maximum Clock Frequency 100 130 85 MHz ns tPHL Propagation Delay STMR to Qn ns ns Symbol Parameter TA = +25°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V M i nM a xM i nM a x tS(H) Setup Time, HIGH or LOW 3.5 4.0 ns tS(L) CS or R/W to STCP 6.0 7.0 tH (H) Hold Time, HIGH or LOW 0 0 tH (L) CS or R/W to STCP 00 tS(H) Setup Time, HIGH or LOW 3.0 3.5 ns tS(L) SI/O to SHCP 3.0 3.5 tH (H) Hold Time, HIGH or LOW 3.0 3.5 tH (L) SI/O to SHCP 3.0 3.5

www.fairchildsemi.com 6 74F673A Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Package Number N24A

7 www.fairchildsemi.com 74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com