74F657 FAIRCHILD | Alldatasheet

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■ 300 Mil 24-pin slimline DIP ■ Combines 74F245 and 74F280A functions in one package ■ 3-STATE outputs ■ B Outputs sink 64 mA ■ 12 mA source current, B side ■ Input diodes for termination effects Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 75F657SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F657SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

www.fairchildsemi.com 2 74F657 Unit Loading/Fan Out Functional Description The Transmit/Receive (T/R) input determines the direction of the data flow through the bidirectional transceivers. Transmit (active HIGH) enables data from the A Port to the B Port; Receive (active LOW) enables data from the B Port to the A Port. The Output Enable (OE ) input disables the parity and ERROR outputs and both the A and B Ports by placing them in a HIGH-Z condition when the Output Enable input is HIGH. When transmitting (T/R HIGH), the parity generator detects whether an even or odd number of bits on the A Port are HIGH and compares these with the condition of the parity select (ODD/EVEN ). If the Parity Select is HIGH and an even number of A inputs are HIGH, the Parity output is HIGH. In receiving mode (T/R LOW), the parity select and number of HIGH inputs on port B are compared to the condition of the Parity input. If an even number of bits on the B Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, then ERROR will be HIGH to indicate no error. If an odd number of bits on the B Port are HIGH, the parity select is HIGH, and the PARITY input is HIGH, the ERROR will be LOW indicating an error. Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL A0–A7 Data Inputs/ 4.5/0.15 90 µA/− 90 µA 3-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) B0–B7 Data Inputs/ 3.5/0.117 70 µA/−70 µA 3-STATE Outputs 600/106.6 (80) −12 mA/64 mA (48 mA) T/R Transmit/Receive Input 2.0/0.067 40 µA/−40 µA OE Enable Input 2.0/0.067 40 µA/−40 µA PARITY Parity Input/ 3.5/0.117 70 µA/−70µA 3-STATE Output 600/106.6 (80) −12 mA/64 mA (48 mA) ODD/EVEN ODD/EVEN Parity Input 1.0/0.033 20 µA/−20 µA ERROR Error Output 600/106.6 (80) −12 mA/64 mA (48 mA) Number of Inputs that are HIGH Inputs Input/ OutputsOutput OE T/R ODD/ Parity ERROR Outputs EVEN Mode 0, 2, 4, 6, 8 L H H H Z Transmit LH L L Z T r a n s m i t LL H H H R e c e i v e LL H L L R e c e i v e LL L H L R e c e i v e LL L L H R e c e i v e 1, 3, 5, 7 L H H L Z Transmit LH L H Z T r a n s m i t LL H H L R e c e i v e LL H L H R e c e i v e LL L H H R e c e i v e LL L L L R e c e i v e Immaterial H X X Z Z Z Inputs Outputs OE T/R L L Bus B Data to Bus A L H Bus A Data to Bus B H X High-Z State

3 www.fairchildsemi.com 74F657 Functional Block Diagram

www.fairchildsemi.com 4 74F657 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.5 VM i n IOH = −1 mA (An) Voltage 10% V CC 2.4 IOH = −3 mA (An Bn, Parity, ERROR) 10% V CC 2.0 IOH = −15 mA (Bn, Parity, ERROR) 5% VCC 2.7 I OH = −1 mA (An) 5% VCC 2.7 IOH = −3 mA (An, Bn, Parity, ERROR) VOL Output LOW 10% V CC 0.5 VM i n IOL = 24 mA (An) Voltage 10% V CC 0.55 IOL = 64 mA (Bn Parity, ERROR) IIH Input HIGH 20 µAM a x VIN = 2.7V (ODD/EVEN) Current 40 VIN 2.7V (T/R, OE) IBVI Input HIGH Current 100 µAV CC = 0V IN = 7.0V (T/R, OE, ODD/EVEN ) Breakdown Test IBVIT Input HIGH Current 1.0 mA Max VIN = 5.5V (Parity, Bn) Breakdown Test (I/O) 2.0 V IN = 5.5V (An) IIL Input LOW −20 µAM a x VIN = 0.5V (ODD/EVEN) Current −40 VIN = 0.5V (T/R, OE) IOZH Output Leakage Current 50 µAM a x VOUT = 2.7V (ERROR) IOZL Output Leakage Current −50 µAM a x V OUT = 0.5V (ERROR) IIH + IOZH Output Leakage 70 µAM a x VI/O = 2.7V (Bn, Parity) Current 90 V I/O = 2.7V (An) IIL + IOZL Output Leakage −70 µAM a x VI/O = 0.5V (Bn, Parity) Current −90 V I/O = 0.5V (An) IOS Output Short-Circuit −60 −150 mA Max VOUT = 0V (An) Current −100 −225 VOUT = 0V (Bn, Parity, ERROR) ICEX Output HIGH Leakage 250 µAM a x VOUT = VCC (ERROR ) Current 1.0 mA Max V OUT = VCC (Bn, Parity) 2.0 mA Max V OUT = VCC (An) IZZ Bus Drainage Test 500 µA0 . 0 V V OUT = 5.25V (An, Bn, Parity, ERROR) ICCH Power Supply Current 101 125 mA Max V O = HIGH ICCL Power Supply Current 112 150 mA Max V O = LOW ICCZ Power Supply Current 109 145 mA Max V O = HIGH Z

5 www.fairchildsemi.com 74F657 Note 3: These delay times reflect the 3-STATE recovery time only and not the signal time through the buffers or the parity check circuity. To assure VALID information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin ≥ (A to PARITY) + (Output Enable Time). Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF C L = 50 pF Min Typ Max Min Max Min Max ns ns

www.fairchildsemi.com 6 74F657 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B

7 www.fairchildsemi.com 74F657 Octal Bidirectional Transceiver with Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com