74F651SPC

54F651SDM NSC | Alldatasheet

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Features

Y Independent registers for A and B buses Y Multiplexed real-time and stored data Y Choice of non-inverting and inverting data paths Ð ’F651 inverting Ð ’F652 non-inverting Y Guaranteed 4000V minimum ESD protection Commercial Military Package Package DescriptionNumber 74F651SPC N24C 24-Lead (0.300 × Wide) Molded Dual-In-Line 54F651SDM (Note 2) J24F 24-Lead (0.300 × Wide) Ceramic Dual-In-Line 74F651SC (Note 1) M24B 24-Lead (0.300 × Wide) Molded Small Outline, JEDEC 54F651FM (Note 2) W24C 24-Lead Cerpack 54F651LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C 74F652SPC N24C 24-Lead (0.300 × Wide) Molded Dual-In-Line 54F652SDM (Note 2) J24F 24-Lead (0.300 × Wide) Ceramic Dual-In-Line 74F652SC (Note 1) M24B 24-Lead (0.300 × Wide) Molded Small Outline, JEDEC 54F652FM (Note 2) W24C 24-Lead Cerpack 54F652LM (Note 2) E28A 24-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13 × reel. Use suffix e SCX Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB Connection Diagrams Pin Assignment DIP, SOIC and Flatpak TL/F/9581–3 Pin Assignment for LCC TL/F/9581–4 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

’F651 TL/F/9581–1 ’F651 TL/F/9581–2 IEEE/IEC ’F652 TL/F/9581–10 ’F652 TL/F/9581–11 Unit Loading/Fan Out 54F/74F Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH/IOL A0 –A7,B 0 –B7 A and B Inputs/ 1.0/1.0 20 mA/b0.6 mA TRI-STATEÉ Outputs 600/106.6 (80) b12 mA/64 mA (48 mA) CPAB, CPBA Clock Inputs 1.0/1.0 20 mA/b0.6 mA SAB, SBA Select Inputs 1.0/1.0 20 mA/b0.6 mA OEAB, OEBA Output Enable Inputs 1.0/1.0 20 mA/b0.6 mA

’F652 TL/F/9581–5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ’F651 TL/F/9581–12 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

In the transceiver mode, data present at the HIGH imped- ance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with the Octal bus transceivers and receivers. Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the appro- priate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforc- es its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. Note A: Real-Time Transfer Bus B to Bus A TL/F/9581–6 OEAB OEBA CPAB CPBA SAB SBA LLX X X L Note B: Real-Time Transfer Bus A to Bus B TL/F/9581–7 OEAB OEBA CPAB CPBA SAB SBA HHXX L X Note C: Storage TL/F/9581–8 OEAB OEBA CPAB CPBA SAB SBA XH L XX X LXX L XX LH LL XX Note D: Transfer Storage Data to A or B TL/F/9581–9 OEAB OEBA CPAB CPBA SAB SBA H L Ho rL Ho rL H X FIGURE 1 Inputs Inputs/Outputs (Note 1) Operating Mode OEAB OEBA CPAB CPBA SAB SBA A 0 thru A 7 B0 thru B 7 L H Ho rL Ho rL X X Input Input Isolation LH LL X X Store A and B Data XH L H or L X X Input Not Specified Store A, Hold B HH LL X X Input Output Store A in Both Registers L X Ho rL L X X Not Specified Input Hold A, Store B LL LL X X Output Input Store B in Both Registers LLX X X L Output Input Real-Time B Data to A Bus L L X H or L X H Store B Data to A Bus HHXX L X Input Output Real-Time A Data to B Bus H H H or L X H X Stored A Data to B Bus H L H or L H or L H H Output Output Stored A Data to B Bus and Stored B Data to A Bus H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial L e LOW to HIGH Clock Transition Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C Ambient Temperature under Bias b55§Ct o a125§C Junction Temperature under Bias b55§Ct o a175§C Plastic b55§Ct o a150§C VCC Pin Potential to Ground Pin b0.5V to a7.0V Input Voltage (Note 2) b0.5V to a7.0V Input Current (Note 2) b30 mA to a5.0 mA Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Voltage Applied to Output in HIGH State (with V CC e 0V) Standard Output b0.5V to V CC TRI-STATE Output b0.5V to a5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Recommended Operating Conditions Free Air Ambient Temperature Military b55§Ct o a125§C Commercial 0 §Ct o a70§C Supply Voltage Military a4.5V to a5.5V Commercial a4.5V to a5.5V Symbol Parameter 54F/74F Units V CC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage b1.2 V Min I IN eb 18 mA (Non I/O Pins) VOH Output HIGH 54F 10% V CC 2.0 V Min IOH eb 12 mA (A n,B n) Voltage 74F 10% V CC 2.0 I OH eb 15 mA (A n,B n) VOL Output LOW 54F 10% V CC 0.55 V Min IOL e 48 mA (A n,B n) Voltage 74F 10% V CC 0.55 I OL e 64 mA (A n,B n) IIH Input HIGH 54F 20.0 mA Max VIN e 2.7V Current 74F 5.0 (Non I/O Pins) IBVI Input HIGH Current 54F 100 mA Max VIN e 7.0V Breakdown Test 74F 7.0 IBVIT Input HIGH Current 54F 1.0 mA Max VIN e 5.5V Breakdown (I/O) 74F 0.5 (A n,B n) ICEX Output HIGH 54F 250 mA Max VOUT e VCC Leakage Current 74F 50 VID Input Leakage 74F 4.75 V 0.0 IID e 1.9 mA Test All Other Pins Grounded IOD Output Leakage 74F 3.75 mA 0.0 VIIOD e 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current b0.6 mA Max V IN e 0.5V (Non I/O Pins) IIH a IOZH Output Leakage Current 70 mA Max V OUT e 2.7V (A n,B n) IIL a IOZL Output Leakage Current b650 mA Max V OUT e 0.5V (A n,B n) IOS Output Short-Circuit Current b100 b225 mA Max V OUT e 0V IZZ Bus Drainage Test 500 mA 0.0V V OUT e 5.25V ICCH Power Supply Current 105 135 mA Max V O e HIGH ICCL Power Supply Current 118 150 mA Max V O e LOW ICCZ Power Supply Current 115 150 mA Max V O e HIGH Z

TA ea 25§C TA,V CC e Mil T A,V CC e ComSymbol Parameter V CC ea 5.0V CL e 50 pF C L e 50 pF Units CL e 50 pF Min Max Min Max Min Max fmax Max. Clock Frequency 90 75 90 MHz AC Operating Requirements 74F 54F 74F Symbol Parameter TA ea 25§C TA,V CC e Mil T A,V CC e Com UnitsVCC ea 5.0V Min Max Min Max Min Max

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 651/652 S C X Temperature Range Family Special Variations 74F e Commercial QB e Military grade device with 54F e Military environmental and burn-in processingDevice Type X e Devices shipped in 13 × reel Package Code Temperature RangeSP e Slim Plastic DIP C e Commercial (0 §Ct o a70§C)SD e Slim Ceramic DIP M e Military ( b55§Ct o a125§C)S e Small Outline (SOIC)

Physical Dimensions inches (millimeters)

28 Lead Ceramic Leadless Chip Carrier, Type C

24 Lead (0.300 × Wide) Ceramic Dual-In-Line Package (SD)

Physical Dimensions inches (millimeters) (Continued) 24 Lead (0.300 × Wide) Molded Small Outline Package, JEDEC (S) 24 Lead (0.300 × Wide) Molded Dual-In-Line Package (SP)

54F/74F651 # 54F/74F652 Transceivers/Registers Physical Dimensions inches (millimeters) (Continued)

24 Lead Cerpack

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor Corporation GmbH Japan Ltd. Hong Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd. 2900 Semiconductor Drive Livry-Gargan-Str. 10 Sumitomo Chemical 13th Floor, Straight Block, Rue Deputado Lacorda Franco Building 16 P.O. Box 58090 D-82256 F 4urstenfeldbruck Engineering Center Ocean Centre, 5 Canton Rd. 120-3A Business Park Drive Santa Clara, CA 95052-8090 Germany Bldg. 7F Tsimshatsui, Kowloon Sao Paulo-SP Monash Business Park Tel: 1(800) 272-9959 Tel: (81-41) 35-0 1-7-1, Nakase, Mihama-Ku Hong Kong Brazil 05418-000 Nottinghill, Melbourne TWX: (910) 339-9240 Telex: 527649 Chiba-City, Tel: (852) 2737-1600 Tel: (55-11) 212-5066 Victoria 3168 Australia Fax: (81-41) 35-1 Ciba Prefecture 261 Fax: (852) 2736-9960 Telex: 391-1131931 NSBR BR Tel: (3) 558-9999 Tel: (043) 299-2300 Fax: (55-11) 212-1181 Fax: (3) 558-9998 Fax: (043) 299-2500 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.