74F651 FAIRCHILD | Alldatasheet
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■ Independent registers for A and B buses ■ Multiplexed real-time and stored data ■ Choice of non-inverting and inverting data paths 74F651 inverting 74F652 non-inverting Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Order Number Package Number Package Description 74F651SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F651SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 74F652SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F652SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
www.fairchildsemi.com 2 74F651 • 74F652 Logic Symbols 74F651 IEEE/IEC 74F651 74F652 IEEE/IEC 74F652 Unit Loading/Fan Out Function Table H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level /c17 = LOW-to-HIGH Clock Transition Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL A0–A7, B0–B7 A and B Inputs/ 1.0/1.0 20 µA/−0.6 mA 3-STATE Outputs 600/106.6 (80) −12 mA/64 mA (48 mA) CPAB, CPBA Clock Inputs 1.0/1.0 20 µA/−0.6 mA SAB, SBA Select Inputs 1.0/1.0 20 µA/−0.6 mA OEAB, OEBA Output Enable Inputs 1.0/1.0 20 µA/−0.6 mA Inputs Inputs/Outputs (Note 1) Operating Mode OEAB OEBA CPAB CPBA SAB SBA A 0 thru A7 B 0 thru B7 L H H or L H or L X X Input Input Isolation LH /c17/c17 X X Store A and B Data XH /c17 H or L X X Input Not Specified Store A, Hold B HH /c17/c17 X X Input Output Store A in Both Registers LX H o r L /c17 X X Not Specified Input Hold A, Store B LL /c17/c17 X X Output Input Store B in Both Registers L L X X X L Output Input Real-Time B Data to A Bus L L X H or L X H Store B Data to A Bus H H X X L X Input Output Real-Time A Data to B Bus H H H or L X H X Stored A Data to B Bus H L H or L H or L H H Output Output Stored A Data to B Bus and Stored B Data to A Bus
3 www.fairchildsemi.com 74F651 • 74F652 Functional Description In the transceiver mode, data present at the HIGH imped- ance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples in Figure 1 demonstrate the four fundamen- tal bus-management functions that can be performed with the Octal bus transceivers and receivers. Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW-to-HIGH transitions at the appropriate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Out- put reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state. Note A: Real-Time Transfer Bus B to Bus A Note B: Real-Time Transfer Bus A to Bus B Note C: Storage Note D: Transfer Storage Data to A or B FIGURE 1. OEAB OEBA CPAB CPBA SAB SBA LLXX X L OEAB OEBA CPAB CPBA SAB SBA HHXX L X OEAB OEBA CPAB CPBA SAB SBA XH /c17 XX X LXX /c17 XX LH /c17/c17 XX OEAB OEBA CPAB CPBA SAB SBA H L H or L H or L H X
www.fairchildsemi.com 4 74F651 • 74F652 Logic Diagrams 74F652 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F651 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
5 www.fairchildsemi.com 74F651 • 74F652 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA (Non I/O Pins) VOH Output HIGH 10% V CC 2.0 V Min I OH = −15 mA (An, Bn) Voltage VOL Output LOW 10% V CC 0.55 V Min I OL = 64 mA (An, Bn) Voltage IIH Input HIGH 5.0 µAM a x VIN = 2.7V Current (Non I/O Pins) IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V Breakdown Test IBVIT Input HIGH Current 0.5 mA Max VIN = 5.5V Breakdown (I/O) (An, Bn) ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V (Non I/O Pins) IIH + IOZH Output Leakage Current 70 µAM a x V OUT = 2.7V (An, Bn) IIL + IOZL Output Leakage Current −650 µAM a x V OUT = 0.5V (An, Bn) IOS Output Short-Circuit Current −100 −225 mA Max V OUT = 0V IZZ Bus Drainage Test 500 µA0 . 0 V V OUT = 5.25V ICCH Power Supply Current 105 135 mA Max V O = HIGH ICCL Power Supply Current 118 150 mA Max V O = LOW ICCZ Power Supply Current 115 150 mA Max V O = HIGH Z
www.fairchildsemi.com 6 74F651 • 74F652 AC Operating Requirements Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF C L = 50 pF Min Max Min Max Min Max fMAX Max. Clock Frequency 90 75 90 MHz ns ns ns ns Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V V CC = +5.0V Min Max Min Max Min Max ns tS(H) Setup Time, HIGH or 5.0 5.0 5.0 ns tS(L) LOW, Bus to Clock 5.0 5.0 5.0 tH (H) Hold Time, HIGH or 2.0 2.5 2.0 ns tH (L) LOW, Bus to Clock 2.0 2.5 2.0 tW (H) Clock Pulse Width 5.0 5.0 5.0 ns tW (L) HIGH or LOW 5.0 5.0 5.0
7 www.fairchildsemi.com 74F651 • 74F652 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
www.fairchildsemi.com 8 74F651 • 74F652 Transceivers/Registers Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com