74F646 FAIRCHILD | Alldatasheet

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■ Independent registers for A and B buses ■ Multiplexed real-time and stored data ■ 74F648 has inverting data paths ■ 74F646/74F646B have non-inverting data paths ■ 74F646B is a faster version of the 74F646 ■ 3-STATE outputs ■ 300 mil slim DIP Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Order Number Package Number Package Description 74F646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F646MSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74F646SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 74F646BSC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F646BSPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide 74F648SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F648SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

www.fairchildsemi.com 2 74F646 • 74F646B • 74F648 Logic Symbols 74F646/74F646B IEEE/IEC 74F646/74F646B 74F648 IEEE/IEC 74F648 Connection Diagrams 74F646/74F646B 74F648

3 www.fairchildsemi.com 74F646 • 74F646B • 74F648 Unit Loading/Fan Out Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Irrelevant /c17 = LOW-to-HIGH Transition Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL A0–A7 Data Register A Inputs/ 3.5/1.083 70 µA/−650 µA 3-STATE Outputs 600/106.6 (80) −12 mA/64 mA (48 mA) B0–B7 Data Register B Inputs/ 3.5/1.083 70 µA/−650 µA 3-STATE Outputs 600/106.6 (80) −12 mA/64 mA (48 mA) CPAB, CPBA Clock Pulse Inputs 1.0/1.0 20 µA/−0.6 mA SAB, SBA Select Inputs 1.0/1.0 20 µA/−0.6 mA G Output Enable Input 1.0/1.0 20 µA/−0.6 mA DIR Direction Control Input 1.0/1.0 20 µA/−0.6 mA Inputs Data I/O (Note 1) Function G DIR CPAB CPBA SAB SBA A 0–A 7 B 0–B 7 H X H or L H or L X X Isolation HX /c17 X X X Input Input Clock A n Data into A Register HXX /c17 X X Clock B n Data into B Register LHXXLX A n to Bn—Real Time (Transparent Mode) LH /c17 X L X Input Output Clock A n Data into A Register L H H or L X H X A Register to B n (Stored Mode) LH /c17 X H X Clock A n Data into A Register and Output to Bn LLXXXL B n to An—Real Time (Transparent Mode) LLX /c17 X L Output Input Clock B n Data into B Register L L X H or L X H B Register to A n (Stored Mode) LLX /c17 X H Clock B n Data into B Register and Output to An

www.fairchildsemi.com 4 74F646 • 74F646B • 74F648 Logic Diagrams 74F646/74F646B Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F648 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

5 www.fairchildsemi.com 74F646 • 74F646B • 74F648 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA (Non I/O Pins) VOH Output HIGH 10% V CC 2.0 V Min I OH = −15 mA (An, Bn) Voltage VOL Output LOW 10% V CC 0.55 V Min I OL = 64 mA (An, Bn) Voltage IIH Input HIGH 5.0 µAM a x V IN = 2.7V (Non I/O Pins) Current IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V (Non I/O Pins) Breakdown Test IBVIT Input HIGH Current 0.5 mA Max V IN = 5.5V (An, Bn) Breakdown (I/O) ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V (Non I/O Pins) IIH + IOZH Output Leakage Current 70 µAM a x V OUT = 2.7V (An, Bn) IIL + IOZL Output Leakage Current −650 µAM a x V OUT = 0.5V (An, Bn) IOS Output Short-Circuit Current −100 −225 mA Max V OUT = 0V IZZ Bus Drainage Test 500 µA0 . 0 V V OUT = 5.25V ICCH Power Supply Current 135 mA Max V O = HIGH ICCL Power Supply Current 150 mA Max V O = LOW ICCZ Power Supply Current 150 mA Max V O = HIGH Z

www.fairchildsemi.com 6 74F646 • 74F646B • 74F648 AC Operating Requirements 74F646/74F648 Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF C L = 50 pF Min Max Min Max Min Max fMAX Maximum Clock Frequency 90 75 90 MHz ns ns ns ns ns ns Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V V CC = +5.0V Min Max Min Max Min Max tS(H) Setup Time, HIGH or LOW 5.0 5.0 5.0 ns tS(L) Bus to Clock 5.0 5.0 5.0 tH (H) Hold Time, HIGH or LOW 2.0 2.5 2.0 ns tH (L) Bus to Clock 2.0 2.5 2.0 tW (H) Clock Pulse Width 5.0 5.0 5.0 ns tW (L) HIGH or LOW 5.0 5.0 5.0

7 www.fairchildsemi.com 74F646 • 74F646B • 74F648 AC Operating Requirements 74F646B Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF C L = 50 pF Min Max Min Max Min Max fMAX Maximum Clock Frequency 165 150 MHz tPLH Propagation Delay 2.5 7.0 2.5 8.0 ns tPHL Clock to Bus 3.0 7.5 3.0 8.0 tPLH Propagation Delay 2.0 6.0 2.0 7.0 ns tPHL Bus to Bus 2.0 6.0 2.0 7.0 tPLH Propagation Delay 2.5 7.5 2.5 8.5 ns tPHL SBA or SAB to A or B 2.5 7.5 2.5 8.5 tPZH Enable Time 2.5 6.5 2.5 8.0 nstPZL OE to A or B 2.5 9.0 2.5 10.0 tPHZ Disable Time 1.5 6.5 1.5 7.5 nstPLZ OE to A or B 2 . 07 . 0 2 . 08 . 5 tPZH Enable Time 2.0 7.0 2.0 8.5 ns tPZL DIR to A or B 3.0 9.5 3.0 10.0 tPHZ Disable Time 1.5 7.5 1.5 8.5 ns tPLZ DIR to A or B 2.5 8.5 2.5 9.5 Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V V CC = +5.0V Min Max Min Max Min Max tS(H) Setup Time, HIGH or LOW 5.0 4.0 ns tS(L) Bus to Clock 5.0 4.0 tH (H) Hold Time, HIGH or LOW 1.5 1.5 ns tH (L) Bus to Clock 1.5 1.5 tW (H) Clock Pulse Width 5.0 5.0 ns tW (L) HIGH or LOW 5.0 5.0

www.fairchildsemi.com 8 74F646 • 74F646B • 74F648 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

9 www.fairchildsemi.com 74F646 • 74F646B • 74F648 Octal Transceiver/Register with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com