74F640 FAIRCHILD | Alldatasheet

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■ Designed for asynchronous two-way data flow between busses ■ Outputs sink 64 mA ■ Transmit/receive (T/R) input controls the direction of data flow ■ 74F645 is a lower power, faster version of the 74F245 ■ 74F640 is an inverting option of the 74F645 Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Order Number Package Number Package Description 74F640SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F640PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74F645PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2 74F640 • 74F645 Unit Loading/Fan Out Functional Description The output enable (OE) is active LOW. If the device is dis- abled (OE HIGH), the outputs are in the high impedance state. The transmit/receive input (T/R) controls whether data is transmitted from the A bus to the B bus or from the B bus to the A bus. When T/R is LOW, B data is sent to the A bus. If T/R is HIGH, A data is sent to the B bus. Function Table H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance State Logic Diagram 74F640 74F645 Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL OE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA T/R Transmit/Receive Input 1.0/1.0 20 µA/−0.6 mA A0–A7 Side A Inputs or 3.5/0.667 70 µA/−0.4 mA 3-STATE Outputs 600/106.6 −12 mA/64 mA B0–B7 Side B Inputs or 3.5/0.667 70 µA/−0.4 mA 3-STATE Outputs 600/106.6 −12 mA/64 mA Inputs Outputs OE T/R 74F640 74F645 L L Bus B data to Bus A Bus B data to Bus A L H Bus A data to Bus B Bus A data to Bus B HX Z Z

3 www.fairchildsemi.com 74F640 • 74F645 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA (Non I/O Pins) VOH Output HIGH 10% V CC 2.0 V Min I OH = −15 mA (An, Bn) Voltage VOL Output LOW 10% V CC 0.55 V Min I OL = 64 mA (An, Bn) Voltage IIH Input HIGH 5.0 µAM a x V IN = 2.7V (Non I/O Pins) Current IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V (Non I/O Pins) Breakdown Test IBVIT Input HIGH Current 0.5 mA Max V IN = 5.5V (An, Bn) Breakdown (I/O) ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V (Non I/O Pins) IIH + IOZH Output Leakage Current 70 µAM a x V OUT = 2.7V (An, Bn) IIL + IOZL Output Leakage Current −650 µAM a x V OUT = 0.5V (An, Bn) IOS Output Short-Circuit Current −100 −225 mA Max V OUT = 0V IZZ Bus Drainage Test 500 µA0 . 0 V V OUT = 5.25 ICCH Power Supply Current (74F640) 80 mA Max V O = HIGH, VIN = 0.2V ICCL Power Supply Current (74F640) 80 mA Max V O = LOW ICCZ Power Supply Current (74F640) 96 mA Max V O = HIGH Z ICCH Power Supply Current (74F645) 65 mA Max V O = HIGH ICCL Power Supply Current (74F645) 80 mA Max V O = LOW, VIN = 0.2V ICCZ Power Supply Current (74F645) 90 mA Max V O = HIGH Z

www.fairchildsemi.com 4 74F640 • 74F645 Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max tPLH Propagation Delay 2.5 7.5 2.0 8.0 ns tPHL A Input to B Output 2.0 7.0 2.0 7.0 tPLH Propagation Delay 2.5 7.5 2.0 8.0 ns tPHL B Input to A Output 2.0 7.0 2.0 7.0 tPZH Enable Time 2.5 7.5 2.0 9.0 ns tPZL OE Input to A Output 2.5 8.0 2.0 8.5 tPHZ Disable Time 1.5 7.0 1.0 7.5 tPLZ OE Input to A Output 1.5 6.0 1.5 6.0 tPZH Enable Time 2.5 7.5 2.0 9.0 ns tPZL OE Input to B Output 2.5 8.0 2.0 8.5 tPHZ Disable Time 1.5 7.0 1.0 7.5 tPLZ OE Input to B Output 1.5 6.0 1.5 6.0 Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max tPLH Propagation Delay 1.5 6.0 1.5 7.0 ns tPHL A Input to B Output 2.0 7.0 2.0 7.5 tPLH Propagation Delay 1.5 6.0 1.5 7.0 ns tPHL B Input to A Output 2.0 7.0 2.0 7.5 tPZH Enable Time 2.5 8.0 2.0 9.0 ns tPZL OE Input to A Output 2.5 8.5 2.0 8.5 tPHZ Disable Time 1.5 7.0 1.0 8.0 tPLZ OE Input to A Output 1.0 5.5 1.0 5.5 tPZH Enable Time 2.5 7.5 2.0 9.5 ns tPZL OE Input to B Output 2.5 8.5 2.5 9.0 tPHZ Disable Time 1.5 6.5 1.0 7.5 tPLZ OE Input to B Output 1.0 5.5 1.0 5.5

5 www.fairchildsemi.com 74F640 • 74F645 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B

www.fairchildsemi.com 6 74F640 • 74F645 Octal Bus Transceiver with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com