74F632QC

DP8406 NSC | Alldatasheet

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Features

Y Detects and corrects single-bit errors Y Detects and flags dual-bit errors Y Built-in diagnostic capability Y Fast write and read cycle processing times Y Byte-write capability Y Guaranteed 4000V minimum ESD protection Y Fully pin and function compatible with TI’s SN74ALS632A thru SN74ALS635 series Simplified Functional Block TL/F/9579–9 Device Package Byte-Write Output DP8406 52-Pin yes TRI-STATE É DP8406 68-Pin yes TRI-STATE É FASTÉ and TRI-STATE É are registered trademarks of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/F/9579–1 Unit Loading/Fan Out 54F/74F Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH/IOL CB0 –CB6 Check Word Bit, Input 3.5/1.083 70 mA/b650 mA or TRI-STATE É Output 150/40 (33.3) b3 mA/24 mA (20 mA) DB0 –DB31 Data Word Bit, Input 3.5/1.083 70 mA/b650 mA or TRI-STATE Output 150/40 (33.3) b3 mA/24 mA (20 mA) OEB0 –OEB3 Output Enable Data Bits 1.0/1.0 20 mA/b0.6 mA LEDBO Output Latch Enable Data Bit 1.0/1.0 20 mA/b0.6 mA OECB Output Enable Check Bit 1.0/1.0 20 mA/b0.6 mA S0,S 1 Select Pins 1.0/1.0 20 mA/b0.6 mA ERR Single Error Flag 50/33.3 b1 mA/20 mA MERR Multiple Error Flag 50/33.3 b1 mA/20 mA Connection Diagrams Pin Assignment for LCC and PCC 52-Pin TL/F/9579–3 Order Number DP8406QV (74F632QC) See NS Package Number V52A Pin Assignment for LCC and PCC 68-Pin TL/F/9579–8NCÐNo internal connection Order Number DP8406V (74F632VC) See NS Package Number V68A

Connection Diagram (Continued) Pin Assignment for Side Brazed DIP TL/F/9579–2 Order Number DP8406D (74F632DC) See NS Package Number D52A Functional Description MEMORY WRITE CYCLE DETAILS During a memory write cycle, the check bits (CB 0 through CB6) are generated internally in the EDAC by seven 16-in- put parity generators using the 32-bit data word as defined in Table II. These seven check bits are stored in memory along with the original 32-bit data word. This 32-bit word will later be used in the memory read cycle for error detection and correction. ERROR DETECTION AND CORRECTION DETAILS During a memory read cycle, the 7-bit check word is re- trieved along with the actual data. In order to be able to determine whether the data from memory is acceptable to use as presented to the bus, the error flags must be tested to determine if they are at the HIGH level. The first case in Table III represents the normal, no-error conditions. The EDAC presents HIGHs on both flags. The next two cases of single-bit errors give a HIGH on MERR and a LOW on ERR , which is the signal for a correctable error, and the EDAC should be sent through the correction cycle. The last three cases of double-bit errors will cause the EDAC to signal LOWs on both ERR and MERR , which is the interrupt indication for the CPU. Error detection is accomplished as the 7-bit check word and the 32-bit data word from memory are applied to internal parity generators/checkers. If the parity of all seven group- ings of data and check bits is correct, it is assumed that no error has occurred and both error flags will be HIGH. TABLE I. Write Control Function Memory EDAC Control DB Control DB Output CB Error Flags Cycle Function S 1 S0 Data I/O OEBn Latch Check I/O Control ERR MERRLEDBO OECB Write Generate L L Input H X Output LH HCheck Word Check Bit * *See Table II for details of check bit generation.

Functional Description (Continued) TABLE II. Parity Algorithm Check Word 32-Bit Data Word Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CB0 XX XX XX X X X X X X X X X X CB1 XXXXXX X X XX X X X X X X CB2 X XX X XX XX X XX X X X X X CB3 XXX XXX XX XXX X X X X X CB4 XX XXXXXX XX X X X X X X CB5 XXXXXXXX XXXXXX X X CB6 XXXXXXXX X X X X X X X X The seven check bits are parity bits derived from the matrix of data bits as indicated by X for each bit. TABLE III. Error Function Total Number of Errors Error Flags Data Correction 32-Bit Data Word 7-Bit Check Word ERR MERR 0 0 H H Not Applicable 1 0 L H Correction 0 1 L H Correction 1 1 L L Interrupt 2 0 L L Interrupt 0 2 L L Interrupt H e HIGH Voltage Level L e LOW Voltage Level If the parity of one or more of the check groups is incorrect, an error has occurred and the proper error flag or flags will be set LOW. Any single error in the 32-bit data word will change the state of either three or five bits of the 7-bit check word. Any single error in the 7-bit check word chang- es the state of only that one bit. In either case, the single error flag (ERR ) will be set LOW while the dual error flag (MERR) will remain HIGH. Any 2-bit error will change the state of an even number of check bits. The 2-bit error is not correctable since the parity tree can only identify single-bit errors. Both error flags are set LOW when any 2-bit error is detected. Three or more simultaneous bit errors can cause the EDAC to believe that no error, a correctable error, or an uncorrect- able error has occurred and will produce erroneous results in all three cases. It should be noted that the gross-error conditions of all LOWs and all HIGHs will be detected. As the corrected word is made available on the data I/O port (DB 0 through DB 31), the check word I/O port (CB 0 through CB 6) presents a 7-bit syndrome error code. This syndrome error code can be used to locate the bad memory chip. See Table V for syndrome decoding. READ-MODIFY-WRITE (BYTE CONTROL) OPERATIONS The ’F632 device is capable of byte-write operations. The 39-bit word from memory must first be latched into the Data Bit and Check Bit input latches. This is easily accomplished by switching from the read and flag mode (S 1 e H, S 0 e L) to the latch input mode (S 1 e H, S 0 e H). The EDAC will then make any corrections, if necessary, to the data word and place it at the input of the output data latch. This data word must then be latched into the output data latch by taking LEDBO from a LOW to a HIGH. Byte control can now be employed on the data word through the OEB 0 through OEB 3 controls. OEB 0 controls DB0 –DB7 (byte 0), OEB 1 controls DB 8 –DB15 (byte 1), OEB2 controls DB 16 –DB23 (byte 2), and OEB 3 controls DB24 –DB31 (byte 3). Placing a HIGH on the byte control will disable the output and the user can modify the byte. If a LOW is placed on the byte control, then the original byte is allowed to pass onto the data bus unchanged. If the original data word is altered through byte control, a new check word must be generated before it is written back into memory. This is easily accomplished by taking controls S 1 and S 0 LOW. Table VI lists the read-modify-write functions. DIAGNOSTIC OPERATIONS The ’F632 is capable of diagnostics that allow the user to determine whether the EDAC or the memory is failing. The diagnostic function tables will help the user to see the possi- bilities for diagnostic control. In the diagnostic mode 1 e L, S 0 e H), the check word is latched into the input latch while the data input latch remains transparent. This lets the user apply various data words against a fixed known check word. If the user applies a diagnostic data word with an error in any bit location, the ERR flag should be LOW. If a diagnostic data word with two errors in any bit location is applied, the MERR flag should be LOW. After the check word is latched into the input latch, it can be verified by taking OECB LOW. This outputs the latched check word. The diagnostic data word can be latched into the output data latch and verified. By changing from the diagnostic mode (S 1 e L, S 0 e H) to the correction mode (S 1 e H, S 0 e H), the user can verify that the EDAC will correct the diagnostic data word. Also, the syndrome bits can be pro- duced to verify that the EDAC pinpoints the error location. Table VII lists the diagnostic functions.

Functional Description (Continued) TABLE IV. Read, Flag and Correct Function Memory EDAC Control DB Control DB Output CB Error Flags Cycle Function S 1 S0 Data I/O OEBn Latch Check I/O Control ERR MERRLEDBO OECB Read Read & Flag H L Input H X Input H Enabled (Note 1) Read Latch Input Latched Latched Data & Check H H Input H L Input H Enabled (Note 1) Bits Data Check Word Read Output Output Output Corrected Data H H Corrected L X Syndrome L Enabled (Note 1) & Syndrome Bits Data Word Bits (Note 2) Note 1: See Table III for error description. Note 2: See Table V for error location. TABLE V. Syndrome Decoding Syndrome Bits Error 6543210 LLLLLLL u n c L L L L L L H 2-Bit L L L L L H L 2-Bit LLLLLH H u n c L L L L H L L 2-Bit LLLLHLH u n c LLLLH HL u n c L L L L H H H 2-Bit (Note 2) L L L H L L L 2-Bit LLLHLLH u n c LLLHLHL D B L L L H L H H 2-Bit LLLH HLL u n c L L L H H L H 2-Bit L L L H H H L 2-Bit LLLH H H H D B L L H L L L L 2-Bit LLHLLLH u n c LLHL LHL D B L L H L L H H 2-Bit LLHLHLL D B 28 L L H L H L H 2-Bit L L H L H H L 2-Bit L LH L HHH D B LLH HLLL D B 26 L L H H L L H 2-Bit L L H H L H L 2-Bit LLH HLH H D B L L H H H L L 2-Bit LLHHHLH D B L L H H H H L unc L L H H H H H 2-Bit Syndrome Bits Error 6543210 L H L L L L L 2-Bit LHL L LLH u n c LHL L LHL D B L H L L L H H 2-Bit LHL LHLL D B 6 L H L L H L H 2-Bit L H L L H H L 2-Bit LHL LHHH D B LHLHLLL D B 4 L H L H L L H 2-Bit L H L H L H L 2-Bit LHLHLH H D B L H L H H L L 2-Bit LHLHHLH D B 2 L H L H H H L unc L H L H H H H 2-Bit LHHL LLL D B 0 L H H L L L H 2-Bit L H H L L H L 2-Bit L H H L L H H unc L H H L H L L 2-Bit LHHLHLH D B LHHLHHLu n c L H H L H H H 2-Bit L H H H L L L 2-Bit L H H H L L H unc L H H H L H L unc L H H H L H H 2-Bit LHHHHL Lu n c L H H H H L H 2-bit L H H H H H L 2-bit LHHHHHH C B CBX e Error in check bit X DBY e Error in data bit Y 2-Bit e Double-bit error unc e Uncorrectable multi-bit error Note: 2-bit and unc condition will cause both ERR and MERR to be LOW Note 1: Syndrome bits for all LOWs. MERR and ERR LOW for all LOWs, only ERR LOW for DB 30 error. Note 2: Syndrome bits for all HIGHs.

Functional Description (Continued) TABLE V. Syndrome Decoding (Continued) Syndrome Bits Error 6543210 H L L L L L L 2-Bit HLL L LLH u n c HLL L LHLu n c H L L L L H H 2-Bit H L L L H L L unc H L L L H L H 2-Bit H L L L H H L 2-Bit H L L L H H H unc HLLHLLLu n c H L L H L L H 2-Bit H L L H L H L 2-Bit HLLHLH H D B H L L H H L L 2-Bit H L L H H L H unc HLLHHHL D B H L L H H H H 2-Bit H L H L L L L unc H L H L L L H 2-Bit H L H L L H L 2-Bit HLHL LHH D B H L H L H L L 2-Bit HLHLHLH D B HLHLHHL D B 11 H L H L H H H 2-Bit H L H H L L L 2-Bit HLHHLLH D B HLHHLHL D B 9 H L H H L H H 2-Bit HLHHHL L D B 8 H L H H H L H 2-Bit H L H H H H L 2-Bit HLHHHHH C B Syndrome Bits Error 6543210 H H L L L L L unc H H L L L L H 2-Bit H H L L L H L 2-Bit HHL L LHH D B H H L L H L L 2-Bit HHL L HLH D B 22 HHL L HHL D B 21 H H L L H H H 2-Bit H H L H L L L 2-Bit HHL H L LH D B HHL H LHL D B 19 H H L H L H H 2-Bit HHL HHL L D B 18 H H L H H L H 2-Bit H H L H H H L 2-Bit HHL HHHH C B H H H L L L L 2-Bit HHH L L LH D B H H H L L H L unc H H H L L H H 2-Bit HHH L HL L D B 17 H H H L H L H 2-Bit H H H L H H L 2-Bit HHH L HHH C B H H H H L L L unc (Note 1) H H H H L L H 2-Bit H H H H L H L 2-Bit HHHH LHH C B H H H H H L L 2-Bit HHHHHLH C B HHHHHHL C B 0 H H H H H H H None CBX e Error in check bit X DBY e Error in data bit Y 2-Bit e Double-bit error unc e Uncorrectable multi-bit error Note: 2-bit and unc condition will cause both ERR and MERR to be LOW Note 1: Syndrome bits for all LOWs. MERR and ERR LOW for all LOWs, only ERR LOW for DB 30 error. Note 2: Syndrome bits for all HIGHs.

Functional Description (Continued) TABLE VI. Read-Modify-Write Function Memory EDAC Control DB Output CB Error Flags Cycle Function S 1 S0 BYTEn* OEBn* Latch Check I/O Control ERR MERRLEDBO OECB Read Read & Flag H L Input H X Input H Enabled Read Latch Input Latched Latched Data & H H Input H L Input H Enabled Check Bits Data Check Word Read Latch Corrected Latched High Z H Data Word into HH Output HH Output L Enabled Output Latch Data Syndrome Word Bits Modify/ Modify Input Write Appropriate Modified H Byte or Bytes LL BYTE0 H Output LH H& Generate New Output Check Word Check Word Unchanged L BYTE0 *OEB0 controls DB 0 –DB7 (BYTE0); OEB 1 controls DB 8 –DB15 (BYTE1); OEB 2 controls DB 16 –DB23 (BYTE2); OEB 3 controls DB 24 –DB31 (BYTE3). TABLE VII. Diagnostic Function EDAC Control DB Byte DB Output CB Error Flags Function S 1 S0 Data I/O Control Latch Check I/O Control ERR MERROEBn LEDBO OECB Read & Flag HL Input Correct HX Input Correct HHData Word Check Bits Latch Input Check Word while Data Input Latched Input Latch L H Diagnostic H L Input H Enabled Remains Data Word * Check Bits Transparent Latch Diagnostic Input Output Data Word into L H Diagnostic H H Latched L Output Latch Data Word * Check Bits Enabled High Z H Latch Diagnostic Latched Output Data Word into HH Input HH Syndrome L EnabledInput Latch Diagnostic Bits Data Word High Z H Output Diagnostic Output Output Data Word & H H Diagnostic L H Syndrome L EnabledSyndrome Bits Data Word Bits High Z H Output Corrected Output Output Diagnostic Data HH Corrected LL Syndrome L EnabledWord & Output Diagnostic Bits Syndrome Bits Data Word High Z H *Diagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case,the diagnostic data word will contain errors in two bit locations.

TL/F/9579–4 Timing Waveforms Read, Flag and Correct Mode TL/F/9579–5

Timing Waveforms (Continued) Read, Correct and Modify Mode TL/F/9579–6 Diagnostic Mode TL/F/9579–7

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C Ambient Temperature under Bias b55§Ct o a125§C Junction Temperature under Bias b55§Ct o a175§C VCC Pin Potential to Ground Pin b0.5V to a7.0V Input Voltage (Note 2) b0.5V to a7.0V Input Current (Note 2) b30 mA to a5.0 mA Voltage Applied to Output in HIGH State (with V CC e 0V) Standard Output b0.5V to V CC TRI-STATE Output b0.5V to a5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions Free Air Ambient Temperature Military b55§Ct o a125§C Commercial 0 §Ct o a70§C Supply Voltage Military a4.5V to a5.5V Commercial a4.5V to a5.5V Symbol Parameter 54F/74F Units V CC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage b1.2 V Min I IN eb 18 mA VOH Output HIGH 54F 10% V CC 2.5 I OH eb 1 mA (ERR , MERR ,D B n,C B n) Voltage 54F 10% V CC 2.4 I OH eb 3m A( D B n,C B n) 74F 10% V CC 2.5 V Min IOH eb 1 mA (ERR , MERR ,D B n,C B n) 74F 10% V CC 2.4 I OH eb 3m A( D B n,C B n) 74F 5% V CC 2.7 I OH eb 1 mA (ERR , MERR ,D B n,C B n) 74F 5% V CC 2.7 I OH eb 3m A( D B n,C B n) VOL Output LOW 54F 10% V CC 0.5 I OL e 20 mA (ERR , MERR ,D B n,C B n) Voltage 74F 10% V CC 0.5 V Min I OL e 20 mA (ERR , MERR ) 74F 10% V CC 0.5 I OL e 24 mA (DB n,C B n) IIH Input HIGH 54F 20.0 mA Max VIN e 2.7V (S 0,S 1, OEB n, OECB , LEDBO ) Current 74F 5.0 IBVI Input HIGH Current 54F 100 mA Max VIN e 7.0V (S 0,S 1, OEB n, OECB , LEDBO ) Breakdown Test 74F 7.0 IBVIT Input HIGH Current 54F 1.0 mA Max VIN e 5.5V (CB n,D B n) Breakdown (I/O) 74F 0.5 ICEX Output HIGH 54F 250 mA Max VOUT e VCC Leakage Current 74F 50 VID Input Leakage 74F 4.75 V 0.0 IID e 1.9 mA Test All Other Pins Grounded IOD Output Leakage 74F 3.75 mA 0.0 VIOD e 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current b0.6 mA Max V IN e 0.5V (S 0,S 1, OEB n, OECB , LEDBO ) IIH a IOZH Output Leakage Current 70 mA Max V I/O e 2.7V (CB n,D B n) IIL a IOZL Output Leakage Current b650 mA Max V I/O e 0.5V (CB n,D B n) IOZH Output Leakage Current 70 mA Max V I/O e 2.7V (CB n,D B n) IOZL Output Leakage Current b650 mA Max V I/O e 0.5V (CB n,D B n) IOS Output Short-Circuit Current b60 b150 mA Max V OUT e 0V IZZ Bus Drainage Test 500 mA 0.0V V OUT e 5.25V (CB n,D B n) ICC Power Supply Current 340 mA Max T A e 0§C–25 §C ICC Power Supply Current 325 mA Max T A e 25§C–70 §C

TA ea 25§C TA,V CC e Mil T A,V CC e ComSymbol Parameter V CC ea 5.0V CL e 50 pF C L e 50 pF Units CL e 50 pF Min Typ Max Min Max Min Max

Symbol Parameter TA ea 25§C TA,V CC e Mil T A,V CC e Com UnitsVCC ea 5.0V Min Max Min Max Min Max ts Setup Time, HIGH or LOW 3.0 3.0 nsDB/CB before S 0 HIGH (S 1 HIGH) ts(H) Setup Time, HIGH 12.0 14.0 nsS0 HIGH before LEDBO HIGH ts(H) Setup Time, HIGH 00 n sLEDBO HIGH before S 0 or S 1 LOW ts(H) Setup Time, HIGH 00 n sLEDBO HIGH before S 1 HIGH ts Setup Time, HIGH or LOW 00 n sDiagnostic DB before S 1 HIGH ts Setup Time, HIGH or LOW Diagnostic CB before 3.0 3.0 ns S

1 LOW or S 0 HIGH

ts Setup Time, HIGH or LOW Diagnostic DB before 8.0 8.0 ns LEDBO HIGH (S 1 LOW, S 0 HIGH) th(L) Hold Time, LOW 8.0 8.0 nsS0 LOW after S 1 HIGH th Hold Time, HIGH or LOW 8.0 8.0 nsDB and CB Hold after S 0 HIGH th Hold Time, HIGH or LOW 8.0 8.0 nsDB Hold after S 1 HIGH th Hold Time, HIGH or LOW 5.0 5.0 nsCB Hold after S 1 LOW or S 0 HIGH th Hold Time, HIGH or LOW Diagnostic DB after 0 0 ns LEDBO HIGH (S 1 LOW, S 0 HIGH) tw(L)* LEDBO Pulse Width 8.0 8.0 ns tcorr* Correction Time 25.0 28.0 ns *Note: These parameters are guaranteed by characterization or other tests performed.

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 632 D C QR Temperature Range Family Special Variations 74F e Commercial FAST QR e Commercial grade device 54F e Military FAST with burn-in QB e Military grade device with Device Type environmental and burn-in processingPackage Code D e Ceramic DIP Temperature Range Q e 52-Lead Plastic Chip Carrier (PCC) C e Commercial (0 §Ct o a70§C) V e 68-Lead Plastic Chip Carrier (PCC) M e Military ( b55§Ct o a125§C) *Order DP8406QV, DP8406V or DP8406D

Physical Dimensions inches (millimeters) 52-Lead Side-Brazed Ceramic Dual-In-Line Package (D) 52-Lead Plastic Chip Carrier (Q)

DP8406 (54F/74F632) 32-Bit Parallel Error Detection and Correction Circuit Physical Dimensions inches (millimeters) (Continued) 68-Lead Plastic Chip Carrier (V) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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