54F573DM NSC | Alldatasheet
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Y Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Y Useful as input or output port for microprocessors Y Functionally identical to ’F373 Y TRI-STATE outputs for bus interfacing Y Guaranteed 4000V minimum ESD protection Commercial Military Package Package DescriptionNumber 74F573PC N20A 20-Lead (0.300 × Wide) Molded Dual-In-Line 54F573DM (Note 2) J20A 20-Lead Ceramic Dual-In-Line 74F573SC (Note 1) M20B 20-Lead (0.300 × Wide) Molded Small Outline, JEDEC 74F573SJ (Note 1) M20D 20-Lead (0.300 × Wide) Molded Small Outline, EIAJ 54F573FM (Note 2) W20A 20-Lead Cerpak 54F573LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13 × reel. Use suffix e SCX and SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols TL/F/9566–1 IEEE/IEC TL/F/9566–4 Connection Diagrams Pin Assignment for DIP, SOIC and Flatpak TL/F/9566–2 Pin Assignment for LCC TL/F/9566–3 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH/IOL D0 –D7 Data Inputs 1.0/1.0 20 mA/b0.6 mA LE Latch Enable Input (Active HIGH) 1.0/1.0 20 mA/b0.6 mA OE TRI-STATE Output Enable Input 1.0/1.0 20 mA/b0.6 mA(Active LOW) O0 –O7 TRI-STATE Latch Outputs 150/40(33.3) b3 mA/24 mA (20 mA) Functional Description The ’F573 contains eight D-type latches with 3-state output buffers. When the Latch Enable (LE) input is HIGH, data on the D n inputs enters the latches. In this condition the latch- es are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3- state buffers are controlled by the Output Enable (OE ) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfer with entering new data into the latches. Function Table Inputs Outputs OE LE D O LH H H LH L L LL X O HX X Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial O0 e Value stored from previous clock cycle Logic Diagram TL/F/9566–5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C Ambient Temperature under Bias b55§Ct o a125§C Junction Temperature under Bias b55§Ct o a175§C Plastic b55§Ct o a150§C VCC Pin Potential to Ground Pin b0.5V to a7.0V Input Voltage (Note 2) b0.5V to a7.0V Input Current (Note 2) b30 mA to a5.0 mA Voltage Applied to Output in HIGH State (with V CC e 0V) Standard Output b0.5V to V CC TRI-STATE Output b0.5V to a5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions Free Air Ambient Temperature Military b55§Ct o a125§C Commercial 0 §Ct o a70§C Supply Voltage Military a4.5V to a5.5V Commercial a4.5V to a5.5V Symbol Parameter 54F/74F Units V CC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage b1.2 V Min I IN eb 18 mA VOH Output HIGH 54F 10% V CC 2.5 I OH eb 1m A Voltage 54F 10% V CC 2.4 I OH eb 3m A 74F 10% V CC 2.5 V Min IOH eb 1m A 74F 10% V CC 2.4 I OH eb 3m A 74F 5% V CC 2.7 I OH eb 1m A 74F 5% V CC 2.7 I OH eb 3m A VOL Output LOW 54F 10% V CC 0.5 V Min IOL e 20 mA Voltage 74F 10% V CC 0.5 I OL e 24 mA IIH Input HIGH 54F 20.0 mA Max VIN e 2.7V Current 74F 5.0 IBVI Input HIGH Current 54F 100 mA Max VIN e 7.0V Breakdown Test 74F 7.0 ICEX Output HIGH 54F 250 mA Max VOUT e VCC Leakage Current 74F 50 VID Input Leakage 74F 4.75 V 0.0 IID e 1.9 mA Test All Other Pins Grounded IOD Output Leakage 74F 3.75 mA 0.0 VIOD e 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current b0.6 mA Max V IN e 0.5V IOZH Output Leakage Current 50 mA Max V OUT e 2.7V IOZL Output Leakage Current b50 mA Max V OUT e 0.5V IOS Output Short-Circuit Current b60 b150 mA Max V OUT e 0V IZZ Bus Drainage Test 500 mA 0.0V V OUT e 5.25V ICCL Power Supply Current 35 55 mA Max V O e LOW ICCZ Power Supply Current 35 55 mA Max V O e HIGH Z
TA ea 25§C TA,V CC e Mil T A,V CC e ComSymbol Parameter V CC ea 5.0V CL e 50 pF C L e 50 pF Units CL e 50 pF Min Typ Max Min Max Min Max AC Operating Requirements 74F 54F 74F Symbol Parameter TA ea 25§C TA,V CC e Mil T A,V CC e Com UnitsVCC ea 5.0V Min Max Min Max Min Max ts(H) Setup Time, HIGH or LOW 2.0 2.0 2.0 ts(L) D n to LE 2.0 2.0 2.0 ns th(H) Hold Time, HIGH or LOW 3.0 3.0 3.0 th(L) D n to LE 3.5 4.0 3.5 tw(H) LE Pulse Width, HIGH 4.0 4.0 4.0 ns
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 573 S C X Temperature Range Family Special Variations 74FeCommercial QB e Military grade device with 54FeMilitary environmental and burn-in processingDevice Type X e Devices shipped in 13 × reels Package Code Temperature RangeP e Plastic DIP CeCommercial (0 §Ct o a70§C)D e Ceramic DIP MeMilitary ( b55§Ct o a125§C)F e Flatpak L e Leadless Chip Carrier (LCC) S e Small Outline SOIC JEDEC SJ e Small Outline SOIC EIAJ Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L)
Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Dual-In-Line Package (D) 20-Lead (0.300 × Wide) Molded Small Outline Package, JEDEC (S)
Physical Dimensions inches (millimeters) (Continued) 20-Lead (0.300 × Wide) Small Outline Package, EIAJ (SJ) 20-Lead (0.300 × Wide) Molded Dual-In-Line Package (P)
54F/74F573 Octal D-Type Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) (Continued)
20 Lead Ceramic Flatpak (F)
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