74F569

74F569 FAIRCHILD | Alldatasheet

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■ Synchronous counting and loading ■ Lookahead carry capability for easy cascading ■ Preset capability for programmable operation ■ 3-STATE outputs for bus organized systems Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram FAST  is a registered trademark of Fairchild Semiconductor Corporation. Order Number Package Number Package Description 74F569SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F569SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F569PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2 74F569 Unit Loading/Fan Out Functional Description The 74F569 counts in the modulo-16 binary sequence. From state 15 it will increment to state 0 in the Up mode; in the Down mode it will decrement from 0 to 15. The clock inputs of all flip-flops are driven in parallel through a clock buffer. All state changes (except due to Master Reset) occurs synchronously with the LOW-to-HIGH transition of the Clock Pulse (CP) input signal. The circuits have five fundamental modes of operation, in order of precedence: asynchronous reset, synchronous reset, parallel load, count and hold. Five control inputs— Master Reset (MR ), Synchronous Reset (SR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle CET)—plus the Up/Down (U/D) input, deter- mine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces the flip-flop Q outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows the Q outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With MR, SR and PE HIGH, CEP and CET permit counting when both are LOW. Conversely, a HIGH signal on either CEP or CET inhibits counting. The 74F569 uses edge-triggered flip-flops and changing the SR, PE, CEP, CET or U/D inputs when the CP is in either state does not cause errors, provided that the recom- mended setup and hold times, with respect to the rising edge of CP , are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC ) output is normally HIGH and goes LOW providing CET is LOW, when the counter reaches zero in the Down mode, or reaches maxi- mum (15) in the Up mode. TC will then remain LOW until a state change occurs, whether by counting or presetting, or until U/D or CET is changed. To implement synchronous multi- stage counters, the connections between the TC output and the CEP and CET inputs can provide either slow or fast carry propagation. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 16 clocks to com- plete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that lim- its the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. For such applications, the Clocked Carry (CC output is provided. The CC output is normally HIGH. When CEP , CET, and TC are LOW, the CC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again, as shown in the CC Truth Table. When the Output Enable (OE) is LOW, the parallel data outputs O0–O 3 are active and follow the flip-flop Q outputs. A HIGH signal on OE forces O0–O 3 to the High Z state but does not prevent counting, loading or resetting. Logic Equations Count Enable = CEP • CET • PE Up: TC = Q0 • Q1 • Q2 • Q3 • (Up) • CET Down: TC = Q0 • Q1 • Q2 • Q3 • (Down) • CET Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL P0–P3 Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA CEP Count Enable Parallel Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA CET Count Enable Trickle Input (Active LOW) 1.0/1.0 20 µA/−1.2 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA PE Parallel Enable Input (Active LOW) 1.0/1.0 20 µA/−1.2 mA U/D Up/Down Count Control Input 1.0/1.0 20 µA/−0.6 mA OE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA MR Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA SR Synchronous Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA O 0–O 3 3-STATE Parallel Data Outputs 150/40(33.3) −3 mA/24 mA (20 mA) TC Terminal Count Output (Active LOW) 50/33.3 −1 mA/20 mA CC Clocked Carry Output (Active LOW) 50/33.3 −1 mA/20 mA

www.fairchildsemi.com 4 74F569 Logic Diagram Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.

5 www.fairchildsemi.com 74F569 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +175°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.5 VM i n IOH = −1 mA (TC, CC, On) Voltage 10% V CC 2.4 I OH = −3 mA (On) 5% VCC 2.7 IOH = −1 mA (TC, CC, On) 5% VCC 2.7 I OH = −3 mA (On) VOL Output LOW 10% V CC 0.5 VM i n IOL = 20 mA (TC, CC) Voltage 10% V CC 0.5 I OL = 24 mA (On) IIH Input HIGH 5.0 µAM a x V IN = 2.7V Current IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V Breakdown Test ICEX Output HIGH 50 µAM a x V OUT = VCC (TC, CC, On) Leakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max VIN = 0.5V (Pn, CEP, CP, U/D, OE, MR, SR) −1.2 mA Max VIN = 0.5V (PE, CET) IOZH Output Leakage Current 50 µAM a x V OUT = 2.7V (On) IOZL Output Leakage Current −50 µAM a x V OUT = 0.5V (On) IOS Output Short-Circuit Current −60 −150 mA Max VOUT = 0V (TC, CC, On) IZZ Bus Drainage Test 500 µA0 . 0 V V OUT = 5.25V (On) ICCH Power Supply Current 45 67 mA Max V O = HIGH ICCL Power Supply Current 45 67 mA Max V O = LOW ICCZ Power Supply Current 45 67 mA Max V O = HIGH Z

www.fairchildsemi.com 6 74F569 Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max fMAX Maximum Clock Frequency 90 70 MHz tPHL Propagation Delay MR to On ns

7 www.fairchildsemi.com 74F569 AC Operating Requirements Symbol Parameter TA = +25°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V M i nM a xM i nM a x tS(H) Setup Time, HIGH or LOW 4.0 4.5 ns tS(L) P n to CP 4.0 4.5 tH (H) Hold Time, HIGH or LOW 3.0 3.5 tH (L) P n to CP 3.0 3.5 tS(H) Setup Time, HIGH or LOW 7.0 8.0 ns tS(L) CEP or CET to CP 5.0 6.5 tH (H) Hold Time, HIGH or LOW 0 0 tH (L) CEP or CET to CP 0.5 0.5 tS(H) Setup Time, HIGH or LOW 8.0 9.0 ns tS(L) PE to CP 8.0 9.0 tH (H) Hold Time, HIGH or LOW 0.0 1.0 tH (L) PE to CP 00 tS(H) Setup Time, HIGH or LOW 11.0 12.5 nstS(L) U/D to CP 7.0 8.5 tH (H) Hold Time, HIGH or LOW 0 0 nstH (L) U/D to CP 00 tS(H) Setup Time, HIGH or LOW 10.5 11.0 ns tS(L) SR to CP 8.5 9.5 tH (H) Hold Time, HIGH or LOW 0 0 tH (L) SR to CP 00 tW (H) CP Pulse Width, 4.0 4.5 ns tW (L) HIGH or LOW 7.0 8.0 tW (L) MR Pulse Width, LOW 4.5 6.0 ns tREC MR Recovery Time 6.0 8.0 ns

www.fairchildsemi.com 8 74F569 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D

9 www.fairchildsemi.com 74F569 4-Bit Bidirectional Counter with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com