74F564 PHILIPS | Alldatasheet
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/C0109 /C0110 /C0114 74F564 Octal D flip-flop (3-State) Product specification 1996 Jan 05 INTEGRATED CIRCUITS IC15 Data Handbook
Philips Semiconductors Product specification 74F564Octal D flip-flop (3-State)
21996 Jan 05 853-0166 16189
FEATURES
- 74F564 is broadside pinout version of 74F534
- Inputs and Outputs on opposite side of package allow easy interface to Microprocessors
- Useful as an Input or Ouput port for Microprocessors
- 3-State Ouputs for Bus interfacing
- Common Output Enable
- 74F574 is a non-inverting version of 74F564
DESCRIPTION
The 74F564 has a broadside pinout configuration to facilitate PC board layout and allows easy interface with microprocessors. It is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE ) control gates. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independently of the register operation. When OE is Low, data in the register appears at the outputs. When OE is High, the outputs are in high impedance “off” state, which means they will neither drive nor load the bus. PIN CONFIGURATION 10 11 20OE GND VCC CP SF01052 Q 0D0 D1 Q 1 D2 Q 2 Q 3D3 Q 4D4 Q 5D5 Q 6D6 Q 7D7 TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F564 180MHz 50mA
ORDERING INFORMATION
VCC = 5V ±10%, Tamb = 0°C to +70°C PKG. DWG # 20-Pin Plastic DIP N74F564N SOT146-1 20-Pin Plastic SOL N74F564D SOT163-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0 - D7 Data inputs 1.0/1.0 20µA/0.6mA OE Output Enable input (active Low) 1.0/1.0 20µA/0.6mA CP Clock Pulse input (active rising edge) 1.0/1.0 20µA/0.6mA Q 0 - Q7 3-State outputs 150/40 3.0mA/24mA LOGIC SYMBOL 345678 141516171819 11 CP OE D0 D1 Q2 Q3 1213 SF01053 VCC =Pin 20 GND=Pin 10 LOGIC SYMBOL (IEEE/IEC) EN1 SF01054
Philips Semiconductors Product specification 74F564Octal D flip-flop (3-State)
1996 Jan 05 3
D Q CP D Q CP Q D CP D Q CP D Q CP D Q CP D Q CP D Q VCC =Pin 20 GND=Pin 10 SF01055 FUNCTION TABLE INPUTS INTERNAL OUTPUTS OPERATING MODES OE CP Dn REGISTER Q 0 – Q7 OPERATING MODES L L l h L H H L Load and read register L ↑ X NC NC Hold H H X Dn NC Dn Z Z Disable outputs H = High voltage level h = High voltage level one setup time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one setup time prior to the Low-to-High clock transition NC= No change X = Don’t care Z = High impedance “off” state ↑ = Low-to-High clock transition = Not a Low-to-High clock transition ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5.0 mA VOUT Voltage applied to output in High output state –0.5 to +VCC V IOUT Current applied to output in Low output state 48 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature –65 to +150 °C
Philips Semiconductors Product specification 74F564Octal D flip-flop (3-State)
1996 Jan 05 4
RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNITSYMBOL PARAMETER MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –3 mA IOL Low-level output current 24 mA Tamb Operating free-air temperature range 0 70 °C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) NO TAG LIMITS SYMBOL PARAMETER TEST CONDITIONS NO TAG MIN TYP NO TAG MAX UNIT VO High level output voltage VCC = MIN, VIL = MAX, ±10%V CC 2.4 V VOH High-level output voltage VCC MIN, VIL MAX, VIH = MIN, IOH = MAX ±5%V CC 2.7 3.4 V VO Low level output voltage VCC = MIN, VIL = MAX, ±10%V CC 0.35 0.50 V VOL Low-level output voltage VCC MIN, VIL MAX, VIH = MIN, IOL = MAX ±5%V CC 0.35 0.50 V VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V II Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –0.6 mA IOZH Off-state output current, High-level voltage applied VCC = MAX, VO = 2.7V 50 µA IOZL Off-state output current, Low-level voltage applied VCC = MAX, VO = 0.5V –50 µA IOS Short-circuit output currentNO TAG VCC = MAX –60 –150 mA ICCH 45 65 mA ICC Supply current (total)ICCL VCC = MAX 50 75 mA ICCZ 55 80 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
Philips Semiconductors Product specification 74F564Octal D flip-flop (3-State)
1996 Jan 05 5
AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C VCC = +5V C L = 50pF, RL = 500Ω Tamb = 0°C to +70°C VCC = +5V ± 10% C L = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX fMAX Maximum Clock frequency Waveform NO TAG 160 180 150 MHz tPLH tPHL Propagation delay CP to Q n Waveform NO TAG 3.5 3.5 5.0 5.0 8.0 8.0 3.0 3.0 8.5 8.5 ns tPZH tPZL Output Enable time to High or Low level Waveform 4 Waveform 5 2.5 4.0 4.5 5.5 7.5 8.0 2.0 3.5 8.0 8.5 ns tPHZ tPLZ Output Disable time from High or Low level Waveform 4 Waveform 5 1.0 1.0 3.0 2.5 6.0 5.5 1.0 1.0 7.0 6.0 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C VCC = +5V C L = 50pF, RL = 500Ω Tamb = 0°C to +70°C VCC = +5.0V ± 10% C L = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX ts(H) ts(L) Setup time, Dn to CP Waveform 3 2.0 2.0 2.0 2.5 ns th(H) th(L) Hold time, Dn to CP Waveform 3 1.0 1.0 1.5 1.5 ns tw (H) tw (L) CP pulse width, High or Low Waveform NO TAG 3.5 3.5 3.5 3.5 ns AC WAVEFORMS For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. tW (H) CP Q n VM VM VM VM VM 1/fMAX tW (L) tPLHtPHL SF01051 Waveform 1. Propagation Delay, Clock and Enable Inputs to Output, Enable, Clock Pulse Widths, and Maximum Clock Frequency VM VM VM tPHL Dn Q n VM tPLH SF00990 Waveform 2. Propagation Delay for Data to Outputs
Philips Semiconductors Product specification 74F564Octal D flip-flop (3-State)
1996 Jan 05 6
AC WAVEFORMS (Continued) For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. CP Dn VM VM VM VM VM VM ts(L)ts(H) th(L)th(H) SF00993 Waveform 3. Data Setup and Hold Times VM VM VM tPHZtPZH OE Q n VOH -0.3V SF00994 Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level VM VM VM tPLZtPZL OE Q n VOL +0.3V SF00995 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORM tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns Input Pulse Definition VCC family 74F D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test Circuit for 3-State Outputs DEFINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = Termination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude 3.0V 1.5V VM R L 7.0V SF00777 TEST SWITCH tPLZ closed tPZL closed All other open SWITCH POSITION
Philips Semiconductors Product specification 74F564Octal D flip-flop (3-State)
1996 Jan 05 7
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
Philips Semiconductors Product specification 74F564Octal D flip-flop (3-State)
1996 Jan 05 8
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
Philips Semiconductors Product specification 74F564Octal D flip-flop (3-State)
1996 Jan 05 9
Philips Semiconductors Product specification 74F564Octal D flip-flop (3-State) Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Date of release: July 1994 Document order number: 9397-750-05138