74F552 FAIRCHILD | Alldatasheet

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■ 8-Bit bidirectional I/O Port with handshake ■ Register status flag flip-flops ■ Separate clock enable and output enable ■ Parity generation and parity check ■ B-outputs sink 64 mA ■ 3-STATE outputs Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for SOIC Pin Assignments for PLCC Order Number Package Number Package Description 74F552SC M28B 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F552QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

www.fairchildsemi.com 2 74F552 Logic Symbols IEEE/IEC Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL A0–A7 A-to-B Port Data Inputs or 3.5/1.083 70 µA/−0.65 mA B-to-A 3-STATE 150/40 (33.3) −3 mA/24 mA (20 mA) B0–B7 B-to-A Transceiver Inputs or 3.5/1.083 70 µA/−0.65 mA A-to-B 3-STATE Output 600/106.6 (80) −12 mA/64 mA (48 mA) FR B Port Flag Output 50/33.3 −1 mA/20 mA FS A Port Flag Output 50/33.3 −1 mA/20 mA PARITY Parity Bit Transceiver Input or Output 3.5/1.083 70 µA/−0.65 mA 600/106.6 (50)−12 mA/64 mA (48 mA) ERROR Parity Check Output (Active LOW) 50/33.3 −1 mA/20 mA CER R Registers Clock Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA CES S Registers Clock Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA CPR R Registers Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA CPS S Registers Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA OEBR B Port and PARITY Output Enable (Active LOW) 1.0/2.0 20 µA/−1.2 mA and Clear FR Input (Active Rising Edge) OEAS A Port Output Enable (Active LOW) 1.0/2.0 20 µA/−1.2 mA and Clear FS Input (Active Rising Edge)

3 www.fairchildsemi.com 74F552 Functional Description Data applied to the A-inputs are entered and stored in the R register on the rising edge of the CPR Clock Pulse, pro- vided that the Clock Enable (CER ) is LOW; simultaneously, the status flip-flop is set and the flag (FR) output goes HIGH. As the Clock Enable (CER) returns to HIGH, the data will be held in the R register. These data entered from the A-inputs will appear at the B Port I/O pins after the Out- put Enable (OEBR ) has gone LOW. When OEBR is LOW, a parity bit appears at the PARITY pin, which will be set HIGH when there is an even number of 1s or all 0s at the Q outputs of the R register. After the data is assimilated, the receiving system clears the flag FR by changing the signal at the OEBR pin from LOW-to-HIGH. Data flow from B-to-A proceeds in the same manner described for A-to-B flow. A LOW at the CES pin and a LOW-to-HIGH transition at CPS pin enters the B-input data and the parity-input data into the S registers and the parity register respectively and set the flag output FS to HIGH. A LOW signal at the OEAS pin enables the A Port I/O pins and a LOW-to-HIGH transition of the OEAS signal clears the FS flag. When OEAS is LOW, the parity check output ERROR will be HIGH if there is an odd number of 1s at the Q outputs of the S registers and the parity register. The flag FS can be cleared by a LOW-to-HIGH transition of the OEAS signal. Register Function Table (Applies to R or S Register) H = HIGH Voltage Level /c17 = LOW-to-HIGH Transition L = LOW Voltage Level † = Not LOW-to-HIGH Transition X = Immaterial NC = No Change Output Control H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance Flag Flip-Flop Function Table (Applies to R or S Flag Flip-Flop) H = HIGH Voltage Level /c17 = LOW-to-HIGH Transition L = LOW Voltage Level † = Not LOW-to-HIGH Transition X = Immaterial NC = No Change Parity Generation Function H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance Parity Check Function H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Inputs Internal Function DC P C E Q XXH N C H o l d D a t a L /c17 LL Load DataH /c17 LH X † L NC Keep Old Data OE Internal A or B Function Q Outputs H X Z Disable Output L L L Enable Output L H H Enable Output Inputs Flag Function CE CP OE Output H X † NC Hold Flag L /c17 †H S e t F l a g XX /c17 L Clear Flag OEBR Number of HIGHs in the Parity OutputQ Outputs of the R Register HX Z L 0, 2, 4, 6, 8 H L 1, 3, 5, 7 L OEAS Number of HIGHs in Parity ERROR the Q Outputs of the S Register Input Output HXX H L 0, 2, 4, 6, 8 L L L 1, 3, 5, 7 L H L 0, 2, 4, 6, 8 H H L 1, 3, 5, 7 H L

www.fairchildsemi.com 4 74F552 Block Diagram

5 www.fairchildsemi.com 74F552 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +175°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode −1.2 V Min IIN = −18 mA Voltage (CER , CES, CPR, CPS, OEBR, OEAS) VOH Output HIGH 10% V CC 2.5 IOH = −1 mA (FR, FS, ERROR, An) Voltage 10% V CC 2.4 I OH = −3 mA (An, Bn PARITY) 10% V CC 2.0 V Min I OH = −15 mA (Bn, PARITY) 5% VCC 2.7 IOH = −1 mA (FR, FS, ERROR, An) 5% VCC 2.7 I OH = −3 mA (An, Bn, PARITY) VOL Output LOW 10% V CC 0.5 IOL = 20 mA (FR, FS, ERROR) Voltage 10% V CC 0.5 V Min I OL = 24 mA (An) 10% V CC 0.55 I OL = 64 mA (Bn, PARITY) IIH Input HIGH 5.0 µAM a x VIN = 2.7V Current (CER , CES, CPR, CPS, OEBR, OEAS) IBVI Input HIGH Current 7.0 µAM a x VIN = 7.0V Breakdown Test (CER , CES, CPR, CPS, OEBR, OEAS) IBVIT Input HIGH Current 0.5 mA Max VIN = 5.5V Breakdown (I/O) (An, Bn, PARITY) ICEX Output HIGH 50 µAM a x VOUT = VCC Leakage Current (FR, FS, ERROR, An, Bn, PARITY) VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All other pins grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All other pins grounded IIL Input LOW Current −0.6 mA Max VIN = 0.5V (CER, CES, CPR, CPS) −1.2 VIN = 0.5V (OEBR, OEAS) IIH + IOZH Output Leakage Current 70 µAM a x V OUT = 2.7V (An, Bn, PARITY) IIL + IOZL Output Leakage Current −650 µAM a x V OUT = 0.5V (An, Bn, PARITY) IOS Output Short- −60 −175 mA Max VOUT = 0V (FR, FS, ERROR, An) Circuit Current −100 −250 V OUT = 0V (Bn, PARITY) IZZ Bus Drainage Test 500 µA0 . 0 V V OUT = 5.25V (An, Bn, PARITY) ICCH Power Supply Current 100 150 mA Max V O = HIGH ICCL Power Supply Current 100 150 mA Max V O = LOW ICCZ Power Supply Current 110 165 mA Max V O = HIGH Z

www.fairchildsemi.com 6 74F552 AC Operating Requirements Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max ns tPLH Propagation Delay CPS or CPR to FS or FR tPHL Propagation Delay OEAS to FS ns ns ns Symbol Parameter TA = +25°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V Min Max Min Max tS(H) Setup Time, HIGH or LOW 7.5 8.5 ns tS(L) A n or Bn or Parity 4.5 5.0 to CPS or CPR tH (H) Hold Time, HIGH or LOW 0 0 tH (L) A n or Bn or Parity 0 0 to CPS or CPR tS(H) Setup, Time HIGH or LOW 6.0 7.0 ns tS(L) CES or CER to CPS or CPR 10.0 11.5 tH (H) Hold Time, HIGH or LOW 0 0 tH (L) CES or CER to CPS or CPR 00 tW (H) Pulse Width, HIGH or LOW 4.0 4.5 ns tW (L) CPS or CPR 6.0 7.0

7 www.fairchildsemi.com 74F552 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M28B

www.fairchildsemi.com 8 74F552 Octal Registered Transceiver with Parity and Flags Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com