74F544

74F544 FAIRCHILD | Alldatasheet

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■ 8-bit octal transceiver ■ Back-to-back registers for storage ■ Separate controls for data flow in each direction ■ A outputs sink 24 mA, B outputs sink 64 mA Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F544SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F544MSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74F544SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide

www.fairchildsemi.com 2 74F544 Unit Loading/Fan Out Functional Description The 74F544 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB input must be LOW in order to enter data from A0–A7 or take data from B0–B7, as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Con- trol of data flow from B to A is similar, but using the CEBA LEBA and OEBA inputs. Data I/O Control Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note: A-to-B data flow shown; B-to-A flow control is the same, except using CEBA , LEBA and OEBA Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL OEAB A-to-B Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA OEBA B-to-A Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA CEAB A-to-B Enable Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA CEBA B-to-A Enable Input (Active LOW) 1.0/2.0 20 µA/−1.2 mA LEAB A-to-B Latch Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA LEBA B-to-A Latch Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA A0–A7 A-to-B Data Inputs or 3.5/1.083 70 µA/−650 µA B-to-A 3-STATE Outputs 150/40(33.3) −3 mA/24 mA (20 mA) B0–B7 B-to-A Data Inputs or 3.5/1.083 70 µA/−650 µA A-to-B 3-STATE Outputs 600/106.6(80) −12 mA/64 mA (48 mA) Inputs Latch Status Output BuffersCEAB LEAB OEAB H X X Latched High Z X H X Latched — L L X Transparent — X X H — High Z L X L — Driving

3 www.fairchildsemi.com 74F544 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min IIN = −18 mA, (except An, Bn) VOH Output HIGH 10% V CC 2.5 VM i n IOH = −1 mA (An) Voltage 10% V CC 2.4 IOH = −3 mA (An, Bn) 10% V CC 2.0 IOH = −15 mA (Bn) 5% VCC 2.7 IOH = −1 mA (An) 5% VCC 2.7 IOH = −3 mA (An, Bn) VOL Output LOW 10% V CC 0.5 VM i n IOL = 24 mA (An) Voltage 10% V CC 0.55 I OL = 64 mA (Bn) IIH Input HIGH 20.0 µAM a x V IN = 2.7V (except An, Bn) Current 5.0 IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V (except An, Bn) Breakdown Test IBVIT Input HIGH Current 0.5 mA Max V IN = 5.5V (An, Bn) Breakdown (I/O) ICEX Output HIGH 250 µAM a x V OUT = VCC (An, Bn) Leakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max VIN = 0.5V (OEAB, OEBA) −1.2 VIN = 0.5V (CEAB, CEBA) IIH + IOZH Output Leakage Current 70 µAM a x VOUT = 2.7V (An, Bn) IIL + IOZL Output Leakage Current −650 µAM a x VOUT = 0.5V (An, Bn) IOS Output Short-Circuit Current −60 −150 mA Max VOUT = 0V (An) −100 −225 VOUT = 0V (Bn) IZZ Bus Drainage Test 500 µA0 . 0 V VOUT = 5.25V (An, Bn) ICCH Power Supply Current 70 105 mA Max V O = HIGH ICCL Power Supply Current 85 130 mA Max V O = LOW ICCZ Power Supply Current 83 125 mA Max V O = HIGH Z

www.fairchildsemi.com 4 74F544 AC Operating Requirements Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF C L = 50 pF Min Typ Max Min Max Min Max An to Bn or Bnto An ns CEBA or CEAB to An or Bn CEBA or CEAB to An or Bn Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V V CC = +5.0V Min Max Min Max Min Max tS(H) Setup Time, HIGH or LOW 3.0 3.0 3.0 ns tS(L) An or Bn to LEBA or LEAB 3.0 3.0 3.0 tH (H) Hold Time, HIGH or LOW 3.0 3.0 3.0 tH (L) An or Bn to LEBA or LEAB 3.0 3.0 3.0 tW (L) Latch Enable, B to A 6.0 9.0 7.5 ns Pulse Width, LOW

5 www.fairchildsemi.com 74F544 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

www.fairchildsemi.com 6 74F544 Octal Registered Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com