74F524 PHILIPS | Alldatasheet
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/C0109 /C0110 /C0114 74F524 8-bit register comparator (open-collector + 3-State) Product specification IC15 Data Handbook
1990 Aug 07
Philips Semiconductors Product specification 74F5248-bit register comparator (open collector + 3-State)
21990 Aug 07 853–0373 00135
FEATURES
- 8-Bit bidirectional register with bus-oriented input-output
- Independent serial input-output to register
- Register bus comparator with ‘equal to’, ‘greater than’ and ‘less than’ outputs
- Cascadable in groups of 8-bits
- Open collector comparator outputs for AND-wired expansion
- Two’s complement or magnitude compare
DESCRIPTION
The 74F524 is an 8-bit bidirectional register with parallel input and output, plus serial input and output progressing from MSB to LSB. All data inputs, serial and parallel, are loaded by the rising edge of the clock. The device functions are controlled by two control lines (S0, S1) to execute shift, load, hold and read out. An 8-bit comparator examines the data stored in the registers and on the data bus. Three true-High, open collector outputs representing ‘register equal to bus’, ‘register greater than bus’ and ‘register less than bus’ are provided. These outputs can be disabled to the OFF state by the use of Status Enable (SE ). A mode control has also been provided to allow Two’s Complement as well as magnitude compare. Linking inputs are provided for expansion to longer words. PIN CONFIGURATION 1110 1S0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O6 I/O7 GND CP M LT C/SO C/SI SE VCC EQ GTI/O5 SF00970 TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F524 65MHz 110mA
ORDERING INFORMATION
VCC = 5V ±10%, Tamb = 0°C to +70°C PKG DWG # 20-pin plastic DIP N74F524N SOT146-1 20-pin plastic SOL N74F524D SOT163-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW I/On Parallel data inputs 3.5/1.0 70µA/0.6mA S0, S1 Mode select inputs 1.0/1.0 20µA/0.6mA C/SI Status priority or serial data input 1.0/1.0 20µA/0.6mA CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.6mA SE Status enable input (active Low) 1.0/1.0 20µA/0.6mA M Compare mode select input 1.0/1.0 20µA/0.6mA I/On 3-state parallel data outputs 150/40 3.0mA/24mA C/SO Status priority or serial data output 50/33 1.0mA/20mA LT Register less than bus output OC/33 OC/20mA EQ Register equal to bus output OC/33 OC/20mA GT Register greater than bus output OC/33 OC/20mA NOTE: OC=Open Collector
Philips Semiconductors Product specification 74F5248-bit register comparator (open collector + 3-State)
1990 Aug 07 3
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CP 12 18 23456789 SF00971 VCC = Pin 20 GND = Pin 10 C/SI17 GT EQ LT C/SO 16 LOGIC SYMBOL (IEEE/IEC) for 74F456 SF00972 & G7 COMP 3, 4D 162D 1,5,6,7>I/O 1,5,6,7<I/O 1,5,6,7=I/O M6 TWO’s COMPLEMENT M5 MAGNITUDE C4/2/4 0=HOLD 1=READ 2=SHIFT 3=LOAD FUNCTIONAL DESCRIPTION The 74F524 contains eight D-type flip-flops connected as a shift register with provision for either parallel or serial loading. Parallel data may be read from or loaded into the registers via the data bus I/O0–I/O7. Serial data is loaded into the register from the C/SI input and may be shifted through the register and out through the C/SO output. Both parallel and serial data entry occurs on the rising edge of the clock (CP). The operation of the shift register is controlled by two signals, S0 and S1, according to the Select Function Table. The 3-State parallel output buffers are enabled only in the READ mode. SELECT FUNCTION TABLE S0 S1 OPERATION L L HOLD–Retains data in shift register L H READ–Read contents in register onto data bus H L SHIFT–Allows serial shifting on next rising clock edge H H LOAD–Load data on bus into register H = High voltage level L = Low voltage level One port of an 8-bit comparator is attached to the data bus while the other port is tied to the outputs of the internal register. Three active-OFF Open Collector outputs indicate whether the contents held in the shift register are ‘greater than’ (GT). ‘less than’ (LT), or ‘equal to’ (EQ) the data on the input bus. A High signal on the Status Enable (SE ) input disables these outputs to the OFF state. A mode control (M) input allows selection between a straightforward magnitude compare or a comparison between Two’s complement numbers. NUMBER REPRESENTATION SELECT TABLE M OPERATION L Magnitude compare H Two’s Complement compare H = High voltage level L = Low voltage level For ‘greater than’ or ‘less than’ detection, the C/SI input must be held High, as indicated in the Function Table. The internal logic is arranged such that a Low signal on the C/SI input places the ‘greater than’ and ‘less than’ outputs in their off state. (Note that this off state serves also as the active state when C/SI is High. It is intended for use in expansion to word lengths greater than 8 bits using multiple 74S524s as explained in the next 3 paragraphs.) The C/SO output will be forced High if the ‘equal to’ status condition exists; otherwise, C/SO will be held Low. Word length expansion (in groups of 8 bits) can be achieved by connecting the C/SO output of the more significant byte to the C/SI input of the next less significant byte and also to its own SE input (see Application Figure 1). The CS/I input of the most significant device is held High while the SE input of the least significant device is held Low. The corresponding status outputs are AND-wired together. In the case of two’s complement number compare, only the Mode input to the most significant device should be High. the Mode inputs to all other cascaded devices are held Low. Suppose that an inequality condition is detected in the most significant device. Assuming that the byte stored in the register is greater than the byte on the data bus, then the EQ and LT outputs will be pulled Low, whereas the GT output will float High. Also, the
1990 Aug 07 4
is established. Typically, this will take 35+6(n–2) ns. Figure 1. Cascading 74F524s for Comparing Longer Words
Philips Semiconductors Product specification 74F5248-bit register comparator (open collector + 3-State)
1990 Aug 07 5
VCC = Pin 20 GND = Pin 10 CP D Q Q CP D Q Q CP D Q Q CP D Q Q CP D Q Q CP D Q Q CP D Q Q CP D Q Q S0 1 SE C/SI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 CP M C/SO EQ GT LT
Philips Semiconductors Product specification 74F5248-bit register comparator (open collector + 3-State)
1990 Aug 07 6
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to +VCC V IO Current applied to output in Low output state All except I/O 40 mA IOUT C urrent applied to output in Low output state I/O only 48 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNITSYMBOL PARAMETER MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA VOH High-level output voltage LT, EQ, GT only 4.5 V IO High level output current Not LT, EQ, GT, C/SO –3 mA IOH High-level output current C/SO only –1 mA IO Low level output current All except I/O 20 mA IOL Low-level output current I/O only 24 mA Tamb Operating free-air temperature range 0 70 °C
Philips Semiconductors Product specification 74F5248-bit register comparator (open collector + 3-State)
1990 Aug 07 7
DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS NO TAG LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS NO TAG MIN TYP 2 MAX UNIT IOH High-level output currentLT, EQ, GT only VCC = MIN, VIL = MAX, VIH = MIN, VOH = MAX 250 µA C/SO only VCC = MIN ±10%V CC 2.5 V VOH High-level output voltage I/On only VCC = MIN , VIL = MAX, V MIN IOH =MAX ±10%V CC 2.4 V I/On only VIH = MIN ±5%V CC 2.7 3.4 V VO Low level output voltage VCC = MIN, VIL= MAX IO = MAX ±10%V CC 0.35 0.50 V VOL Low-level output voltage VIL = MAX , VIH = MIN IOL = MAX ±5%V CC 0.35 0.50 V VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V II Input current at maximumI/On VCC = MAX, VI = 5.5V 1 mA II input voltage Except I/On VCC = MAX, VI = 7.0V 100 µA IIH High-level input current Except I/On VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current Except I/On VCC = MAX, VI = 0.5V –0.6 mA IOZH Off-state output current High-level voltage applied I/On only VCC = MAX, VO = 2.7V 70 µA IOZL Off-state output current Low-level voltage applied I/On only VCC = MAX, VO = 0.5V –0.6 mA IOS Short-circuit output current Except LT, EQ, GT VCC = MAX –60 –150 mA ICC Supply current (total) VCC = MAX 110 150 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
Philips Semiconductors Product specification 74F5248-bit register comparator (open collector + 3-State)
1990 Aug 07 8
AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5V Tamb = +25°C C L = 50pF, RL = 500Ω VCC = +5V ± 10% Tamb = 0°C to +70°C C L = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX fMAX Maximum clock frequency Waveform 4 50 65 45 MHz tPLH tPHL Propagation delay I/On to EQ Waveform 2 9.0 4.5 11.5 7.5 17.0 11.0 9.0 4.5 18.0 12.0 ns tPLH tPHL Propagation delay I/On to GT Waveform 2 8.5 6.5 11.0 9.5 17.0 15.5 8.5 6.5 18.0 16.5 ns tPLH tPHL Propagation delay I/On to LT Waveform 2 8.0 6.0 11.0 10.5 17.0 14.0 8.0 6.0 18.0 15.0 ns tPLH tPHL Propagation delay I/On to C/SO Waveform 2 7.0 6.5 13.0 9.0 16.0 14.0 7.0 5.5 17.0 15.0 ns tPLH tPHL Propagation delay CP to EQ Waveform 4 11.0 4.0 17.0 8.0 22.0 14.0 10.0 4.0 23.0 15.0 ns tPLH tPHL Propagation delay CP to GT Waveform 4 11.0 10.0 16.0 16.5 20.0 21.0 10.0 10.0 21.0 22.0 ns tPHL tPLH Propagation delay CP to LT Waveform 4 11.0 8.0 16.0 14.0 23.0 18.0 10.0 8.0 24.0 19.0 ns tPLH Propagation delay CP to C/SO (Load) tPLH tPHL Propagation delay CP to C/SO (Serial shift) Waveform 4 5.0 4.5 10.0 9.0 13.0 11.5 5.0 4.5 14.0 12.5 ns tPLH tPHL Propagation delay C/SI to GT Waveform 1 8.0 3.0 10.5 4.5 16.0 8.5 9.0 2.5 17.0 9.5 ns tPLH tPHL Propagation delay C/SI to LT Waveform 1 8.0 3.0 10.5 6.0 17.0 8.5 8.0 2.5 18.0 9.5 ns tPLH tPHL Propagation delay Sn to C/SO Waveform 2 6.5 5.5 8.0 10.0 14.5 17.0 6.5 5.5 15.5 18.0 ns tPLH tPHL Propagation delay SE to EQ Waveform 2 3.5 2.5 7.0 4.5 10.5 8.0 3.5 2.5 11.5 9.0 ns tPLH tPHL Propagation delay SE to GT Waveform 2 6.0 3.5 8.0 5.0 13.0 8.0 6.0 3.0 14.0 9.0 ns tPLH tPHL Propagation delay SE to LT Waveform 2 5.0 3.5 8.0 5.5 12.0 8.0 5.0 3.0 13.0 9.0 ns tPLH tPHL Propagation delay C/SI to C/SO Waveform 2 4.0 4.0 7.0 7.0 11.0 11.0 4.0 4.0 12.0 12.0 ns tPLH tPHL Propagation delay M to GT Waveform 2 8.0 8.0 13.0 10.0 18.0 15.5 8.0 8.0 19.0 16.5 ns tPLH tPHL Propagation delay M to LT Waveform 2 10.0 6.0 15.0 8.0 20.0 12.0 10.0 5.0 21.0 13.0 ns tPZH tPZL Output Enable time Sn to I/On Waveform NO TAG Waveform NO TAG 4.5 5.5 7.0 9.0 13.0 15.0 4.5 5.5 14.0 16.0 ns tPHZ tPLZ Output Disable time Sn to I/On Waveform NO TAG Waveform NO TAG 3.0 4.5 5.0 8.0 12.0 12.5 2.0 4.5 13.0 13.5 ns
Philips Semiconductors Product specification 74F5248-bit register comparator (open collector + 3-State)
1990 Aug 07 9
Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX ts(H) ts(L) Setup time, High or Low I/On to CP Waveform 3 6.0 6.0 6.0 6.0 ns th(H) th(L) Hold time, High or Low I/On to CP Waveform 3 0 ns ts(H) ts(L) Setup time, High or Low S0, S1 to CP Waveform 3 13.5 10.0 15.0 10.0 ns th(H) th(L) Hold time, High or Low S0, S1 to CP Waveform 3 0 ns ts(H) ts(L) Setup time, High or Low C/SI to CP Waveform 3 7.0 7.0 7.0 7.0 ns th(H) th(L) Hold time, High or Low C/SI to CP Waveform 3 0 ns tw (H) tw (L) CP pulse width, High or Low Waveform 4 5.0 10.0 5.0 10.0 ns AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. SF00974 VM VM VM VM tPHL tPLH C/SI GT, LT Waveform 1. Propagation Delay for Inverting Outputs SF00975 VM VM VM VM tPHL tPLH SE , C/SI, M I/On, Sn EQ, C/SO GT, LT Waveform 2. Propagation Delay for Non-Inverting Outputs VM VM VM VM VM VM ts(L) t h(L)ts(H) t h(H) C/SI, I/On, Sn CP SF00976 Waveform 3. Setup and Hold Times VM tPLHtPHL VM VM VM 1/fMAX tW (L) SF00977 tW (H) EQ, C/SO, GT, LT CP Waveform 4. Propagation Delay, Clock to Output, Clock Pulse Width, and Maximum Clock Frequency
Philips Semiconductors Product specification 74F5248-bit register comparator (open collector + 3-State)
1990 Aug 07 10
AC WAVEFORMS (Continued) For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. VM VM VM tPHZtPZH VOH -0.3V Sn SF00978 I/On Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level VM VM VM tPLZtPZL VOL +0.3V Sn SF00979 I/On Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND WAVEFORMS tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns Input Pulse Definition VCC family 74F D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test Circuit for 3-State Outputs and Open Collector Outputs DEFINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = Termination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude 3.0V 1.5V VM R L 7.0V SF00980 TEST SWITCH tPLZ, tPZL closed Open Collector closed All other open SWITCH POSITION
Philips Semiconductors Product specification 74F5248-bit register comparator (open-collector + 3-State)
1990 Aug 07 11
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
Philips Semiconductors Product specification 74F5248-bit register comparator (open-collector + 3-State)
1990 Aug 07 12
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
Philips Semiconductors Product specification 74F5248-bit register comparator (open-collector + 3-State)
1990 Aug 07 13
Philips Semiconductors Product specification 74F5248-bit register comparator (open-collector + 3-State) yyyy mmm dd 14 Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors
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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Date of release: 10-98 Document order number: 9397-750-05131 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.