74F524

74F524 FAIRCHILD | Alldatasheet

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Features

■ 8-Bit bidirectional register with bus-oriented input-output ■ Independent serial input-output to register ■ Register bus comparator with “equal to”, “greater than” and “less than” outputs ■ Cascadable in groups of eight bits ■ Open-collector comparator outputs for AND-wired expansion ■ Twos complement or magnitude compare Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F524SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F524PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2 74F524 Unit Loading/Fan Out Note 1: OC = Open Collector Number Representation Select Table Select Truth Table Status Truth Table (Hold Mode) 1 = HIGH if data are equal, otherwise LOW H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL S0, S1 Mode Select Inputs 1.0/1.0 20 µA/−0.6 mA C/SI Status Priority or Serial Data Input 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA SE Status Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA M Compare Mode Select Input 1.0/1.0 20 µA/−0.6 mA I/O0–I/O7 Parallel Data Inputs or 3.5/1.083 70 µA/−0.65 mA 3-STATE Parallel Data Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) C/SO Status Priority or Serial Data Output 50/33.3 −1 mA/20 mA LT Register Less Than Bus Output OC (Note 1) /33.3 (Note 1) /20 mA EQ Register Equal Bus Output OC(Note 1) /33.3 (Note 1) /20 mA GT Register Greater Than Bus Output OC(Note 1) /33.3 (Note 1) /20 mA MO p e r a t i o n L Magnitude Compare H Twos Complement Compare S

0 S1 Operation

L L Hold—Retains Data in Shift Register L H Read—Read Contents in Register onto Data Bus, Data Remains in Register Unaffected by Clock H L Shift—Allows Serial Shifting on Next Rising Clock Edge H H Load—Load Data on Bus into Register Inputs Outputs SE C/SI Data Comparison EQ GT LT C/SO HH X HHH1 LL O A–O H > I/O0–I/O7 LHHL XL O A–O H = I/O0–I/O7 HHHL HL O A–O H < I/O0–I/O7 LHHL HH O A–O H > I/O0–I/O7 LHLL HH O A–O H = I/O0–I/O7 HLLH LH O A–O H < I/O0–I/O7 LLHL

lel output buffers are enabled only in the Read mode. must be held HIGH, as indicated in the Status Truth Table. for word length greater than eight bits. Mode inputs to all other cascaded devices are held LOW. the EQ and GT outputs go LOW and LT output floats HIGH. this will take 35 + 6(n−2) ns. FIGURE 1. Cascading 74F524s for Comparing Longer Words

www.fairchildsemi.com 4 74F524 Block Diagram Notes: 1. 3-STATE Output 2. Open-Collector Output

5 www.fairchildsemi.com 74F524 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.5 VM i n IOH = −1 mA Voltage 10% V CC 2.4 I OH = −3 mA 5% V CC 2.7 I OH = −1 mA 5% V CC 2.7 I OH = −3 mA VOL Output LOW 10% V CC 0.5 VM i n IOL = 20 mA (I/On) Voltage 10% V CC 0.5 I OL = 24 mA (LT, GT, EQ, C/SO) IIH Input HIGH Current 5.0 µAM a x V IN = 2.7V IBVI Input HIGH Current 7.0 µAM a x VIN = 7.0V Breakdown Test ICEX Output HIGH 50 µAM a x VOUT = VCC (I/On, C/SO) Leakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V IIH + IOZH Output Leakage Current 70 µAM a x V I/O = 2.7V IIL + IOZL Output Leakage Current −650 µAM a x V I/O = 0.5V IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V IOHC Open Collector, Output 250 µAM i n V OUT = VCCOFF Leakage Test ICCH Power Supply Current 128 180 mA Max V O = HIGH ICCL Power Supply Current 128 180 mA Max V O = LOW ICCZ Power Supply Current 128 180 mA Max V O = HIGH Z

www.fairchildsemi.com 6 74F524 Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max fMAX Maximum Shift Frequency 50 75 50 MHz ns ns ns tPLH Propagation Delay CP to C/SO (Load) ns ns ns ns ns ns ns

7 www.fairchildsemi.com 74F524 AC Operating Requirements Symbol Parameter TA = +25°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V Min Max Min Max tS(H) Setup Time, HIGH or LOW 6.0 6.0 tS(L) I/O n to CP 6.0 6.0 ns tH (H) Hold Time, HIGH or LOW 0 0 tH (L) I/O n to CP 0 0 tS(H) Setup Time, HIGH or LOW 10.0 10.0 tS(L) S 0 or S1 to CP 10.0 10.0 ns tH (H) Hold Time, HIGH or LOW 0 0 tH (L) S 0 or S1 to CP 0 0 tS(H) Setup Time, HIGH or LOW 7.0 7.0 tS(L) C/SI to CP 7.0 7.0 ns tH (H) Hold Time, HIGH or LOW 0 0 tH (L) C/SI to CP 0 0 tW (H) Clock Pulse Width, HIGH 5.0 5.0 ns

www.fairchildsemi.com 8 74F524 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B

9 www.fairchildsemi.com 74F524 8-Bit Registered Comparator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com