54F413DM NSC | Alldatasheet

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Y Separate input and output clocks Y Parallel input and output Y Expandable without external logic Y 15 MHz data rate Y Supply current 160 mA max Y Available in SOIC, (300 mil only) Commercial Military Package Package DescriptionNumber 74F413PC N16E 16-Lead (0.300 × Wide) Molded Dual-In-Line 54F413DM (Note 1) J16A 16-Lead Ceramic Dual-In-Line Note 1: Military grade device with environmental and burn-in processing. Use suffix e DMQB. Logic Symbol TL/F/9541–1 Connection Diagram Pin Assignment for DIP TL/F/9541–2 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH/IOL D0 –D3 Data Inputs 1.0/0.667 20 mA/b0.4 mA O0 –O3 Data Outputs 50/13.3 b1 mA/8 mA IR Input Ready 1.0/0.667 20 mA/b0.4 mA SI Shift In 1.0/0.667 20 mA/b0.4 mA SO Shift Out 1.0/0.667 20 mA/b0.4 mA OR Output Ready 1.0/0.667 20 mA/b0.4 mA MR Master Reset 1.0/0.667 20 mA/b0.4 mA Functional Description Data InputÐ Data is entered into the FIFO on D 0 –D3 in- puts. To enter data the Input Ready (IR) should be HIGH, indicating that the first location is ready to accept data. Data then present at the four data inputs is entered into the first location when the Shift In (SI) is brought HIGH. An SI HIGH signal causes the IR to go LOW. Data remains at the first location until SI is brought LOW. When SI is brought LOW and the FIFO is not full, IR will go HIGH, indicating that more room is available. Simultaneously, data will propagate to the second location and continue shifting until it reaches the output stage or a full location. If the memory is full, IR will remain LOW. Data TransferÐ Once data is entered into the second cell, the transfer of any full cell to the adjacent (downstream) empty cell is automatic, activated by an on-chip control. Thus data will stack up at the end of the device while empty locations will ‘‘bubble’’ to the front. The t PT parameter de- fines the time required for the first data to travel from input to the output of a previously empty device. Data OutputÐ Data is read from the O 0 –O3 outputs. When data is shifted to the output stage, Output Ready (OR) goes HIGH, indicating the presence of valid data. When the OR is HIGH, data may be shifted out by bringing the Shift Out (SO) HIGH. A HIGH signal at SO causes the OR to go LOW. Valid data is maintained while the SO is HIGH. When SO is brought LOW, the upstream data, provided that stage has valid data, is shifted to the output stage. When new valid data is shifted to the output stage, OR goes HIGH. If the FIFO is emptied, OR stays LOW, and O 0 –O3 remains as before, i.e., data does not change if FIFO is empty. Input Ready and Output Ready may also be used as status signals indicating that the FIFO is completely full (In- put Ready stays LOW for at least t PT) or completely empty (Output Ready stays LOW for at least t PT). Block Diagram TL/F/9541–4

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C Ambient Temperature under Bias b55§Ct o a125§C Junction Temperature under Bias b55§Ct o a175§C Plastic b55§Ct o a150§C VCC Pin Potential to Ground Pin b0.5V to a7.0V Input Voltage (Note 2) b0.5V to a7.0V Input Current (Note 2) b30 mA to a5.0 mA Voltage Applied to Output in HIGH State (with V CC e 0V) Standard Output b0.5V to V CC TRI-STATEÉ Output b0.5V to a5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions Free Air Ambient Temperature Military b55§Ct o a125§C Commercial 0 §Ct o a70§C Supply Voltage Military a4.5V to a5.5V Commercial a4.5V to a5.5V Symbol Parameter 54F/74F Units V CC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage b1.5 V Min I IN eb 18 mA VOH Output HIGH 54F 10% V CC 2.4 I OH eb 1m A Voltage 74F 10% V CC 2.4 V Min I OH eb 1m A 74F 5% V CC 2.7 I OH eb 1m A VOL Output LOW 54F 10% V CC 0.5 V Min IOL e 8m A Voltage 74F 10% V CC 0.5 I OL e 8m A IIH Input HIGH 54F 20.0 mA Max V IN e 2.7VCurrent 74F 5.0 IBVI Input HIGH Current 54F 100 mA Max V IN e 7.0VBreakdown Test 74F 7.0 ICEX Output HIGH 54F 250 mA Max V OUT e VCCLeakage Current 74F 50 VID Input Leakage 74F 4.75 V 0.0 IID e 1.9 mA Test All Other Pins Grounded IOD Output Leakage 74F 3.75 mA 0.0 VIOD e 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current b0.4 mA Max V IN e 0.5V IOS Output Short-Circuit Current b20 b130 mA Max V OUT e 0V ICCH Power Supply Current 115 160 mA Max V O e HIGH

TA ea 25§C TA,V CC e Mil T A,V CC e ComSymbol Parameter V CC ea 5.0V CL e 50 pF C L e 50 pF Units CL e 50 pF Min Typ Max Min Max Min Max fmax Shift In Rate 10 8.0 10 MHz fmax Shift Out Rate 10 8.0 10 MHz AC Operating Requirements 74F 54F 74F Symbol Parameter TA ea 25§C TA,V CC e Mil T A,V CC e Com UnitsVCC ea 5.0V Min Max Min Max Min Max ts(H) Setup Time, HIGH or LOW 1.0 1.0 1.0 ts(L) D n to SI 1.0 1.0 1.0 ns th(H) Hold Time, HIGH or LOW 10.0 10.0 10.0 th(L) D n to SI 10.0 10.0 10.0 tw(H) Shift In Pulse Width 5.0 5.0 5.0 tw(L) HIGH or LOW 10.0 10.0 10.0 ns tw(H) Shift Out Pulse Width 7.5 8.5 7.5 tw(L) HIGH or LOW 10.0 10.0 10.0 tw(H) Input Ready Pulse Width, 7.5 8.5 7.5 nsHIGH tw(L) Output Ready Pulse Width, 5.0 5.0 5.0 nsLOW tw(L) Master Reset Pulse Width, 10.0 10.0 10.0 nsLOW trec Recovery Time, MR to SI 32.0 35.0 35.0 ns tPT Data Throughput Time 0.9 1.0 1.0 ms

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 413 P C X Temperature Range Family Special Variations 74F e Commercial QB e Military grade device with 54F e Military environmental and burn-in processingDevice Type Temperature RangePackage Code C e Commercial (0 §Ct o a70§C)P e Plastic DIP M e Military ( b55§Ct o a125§C)D e Ceramic DIP Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (D)

54F/74F413 6 4 x 4 First-In First-Out Buffer Memory with Parallel I/O Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.300 × Wide) Molded Dual-In-Line Package (P) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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