74F410 PHILIPS | Alldatasheet

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Technical content

Philips Semiconductors FAST Products Product specification 74F410Register stack – 16×4 RAM 3-State output register 1January 8, 1990 853-1310 98498

FEATURES

  • Edge triggered output register
  • ypical access time of 19.5ns
  • Optimize for register stack operation
  • 3–state outputs
  • 18–pin package

DESCRIPTION

The 74F410 is a register oriented high speed 64–bit read/write memory organized as 16–words by 4–bits. An edge–triggered 4–bit output register allows new input data to be written while previous data is held. 3–state outputs are provided for maximum versatility. The 74F410 is fully compatible with all TTL families. TYPE TYPICAL ACCESS TIME TYPICAL SUPPLY CURRENT ( TOTAL) 74F410 19.5ns 45mA FUNCTIONAL DESCRIPTION Write operation – When the three control inputs, write enable (WE), chip select (CS), and clock (CP), are low the information on the data inputs (D0–D3) is written into the memory location selected by the address inputs (A0–A3). If the input data changes while WE, CS, and CP are low, the contents of the selected memory location follow these changes provided setup and hold time criteria are met. Read operation – When CS is low, WE is high, and CP goes from low–to–high, the contents of the memory location selected by the address inputs (A0–A3) are edge– triggered into the output register. When WE is low, CS is low, CP goes from low–to–high, the data at the data inputs is edge–triggered into the output register. The OE input controls the output buffers. When OE is high the four outputs (Q0–Q3) are in a high impedance or off state; when OE is low, the outputs are determined by the state of the output register.

ORDERING INFORMATION

DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 18–pin plastic DIP (300mil) N74F410N INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0 – D3 Data inputs 1.0/1.0 20µA/0.6mA A0 – A3 Address inputs 1.0/1.0 20µA/0.6mA CP Clock pulse input (active rising edge) 1.0/2.0 20µA/1.2mA CS Chip select input (active low) 1.0/2.0 20µA/1.2mA OE Output enable input (active low) 1.0/1.0 20µA/0.6mA WE Write enable input (active low) 1.0/1.0 20µA/0.6mA Q0 – Q3 Data outputs 150/40 3mA/24mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. PIN CONFIGURATION LOGIC SYMBOL IEC/IEEE SYMBOL 127 CS WE CP OE 11 10 D0 D2 D3D1 Q0 Q1 Q2 Q3 16 14 12 10 15 13 11 118 VCC VCC = Pin 18 GND = Pin 9 CS WE CP OE 13 12 15 14 17 16 A1,2D A3 A 0 Q3GND 109 EN3

Philips Semiconductors FAST Products Product specification 74F410Register stack – 16×4 RAM 3-State output register January 8, 1990 2 LOGIC DIAGRAM VCC = pin GND = pin 9 Address decoder RAM16 4D0 Data inputs 16 Register WE CS CP OE ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in high output state –0.5 to VCC V IOUT Current applied to output in low output state 48 mA Tamb Operating free air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C

Philips Semiconductors FAST Products Product specification 74F410Register stack – 16×4 RAM 3-State output register January 8, 1990 3 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS T A t o C UNIT MIN NOM MAX VCC Supply voltage 4.5 5.0 5.5 V VIH High–level input voltage 2.0 V VIL Low–level input voltage 0.8 V IIk Input clamp current –18 mA IOH High–level output current –3 mA IOL Low–level output current 24 mA Tamb Operating free air temperature range 0 +70 °C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS 1 LIMITS UNIT MIN TYP 2 MAX VOH High-level output voltage VCC = MIN, VIL = MAX ±10%V CC 2.4 V VIH = MIN, IOH = MAX ±5%V CC 2.7 V VOL Low-level output voltage VCC = MIN, VIL = MAX ±10%V CC 0.35 0.50 V VIH = MIN, IOL = MAX ±5%V CC 0.35 0.50 V VIK Input clamp voltage VCC = MIN, II = IIK -0.73 -1.2 V II Input current at maximum input voltageVCC = MAX, VI = 7.0V 100 µA IIH High–level input current VCC = MAX, VI = 2.7V 20 µA IIL Low–level input current others VCC = MAX, VI = 0.5V -0.6 mA CP, CS -1.2 mA IOZH Offset–output current, high–level voltage applied VCC = MAX, VI = 2.7V 50 µA IOZL Offset–output current, low–level voltage applied VCC = MAX, VI = 0.5V –50 µA IOS Short-circuit output current3 VCC = MAX -60 -150 mA ICC Supply current (total) VCC = MAX 45 70 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.

Philips Semiconductors FAST Products Product specification 74F410Register stack – 16×4 RAM 3-State output register January 8, 1990 4 AC ELECTRICAL CHARACTERISTICS LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX tPLH tPHL Propagation dealy CP to Qn Waveform 1 4.0 4.5 6.5 6.5 8.5 9.0 3.5 4.0 9.5 10.0 ns tPZH tPZL Output enable time OE to Qn Waveform 3, 4 3.0 4.5 4.5 6.0 7.5 9.0 2.5 3.5 8.5 9.5 ns tPHZ tPHL Output disable time OE to Qn Waveform 3, 4 2.0 2.0 3.5 3.5 6.0 6.5 1.5 2.0 6.5 7.0 ns AC SETUP REQUIREMENTS FOR READ MODE LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX tsu(L) Setup time, low, CS to CP1 Waveform 1 4.0 4.5 ns th(L) Hold time, low, CS to CP1 Waveform 1 3.5 4.5 ns tsu(H) tsu(L) Setup time, high or low An to CP1 Waveform 1 13.0 13.0 15.0 15.0 ns th(H) th(L) Hold time, high or low An to CP1 Waveform 1 0 0 ns tsu(H) Setup time, high, WE to CP1 Waveform 1 13.0 15.0 ns th(H) Hold time, high, WE to CP1 Waveform 1 0 0 ns tw (L) CP pulse width, low Waveform 1 5.0 6.0 ns NOTE: 1. Low–to–high clock transition. AC SETUP REQUIREMENTS FOR WRITE MODE LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX tsu(H) tsu(L) Setup time, high or low An to WE, CS, CP Waveform 2 0 0 ns th(H) th(L) Hold time, high or low An to WE, CS, CP Waveform 2 0 0 ns tsu(H) tsu(L) Setup time, high or low Dn to WE, CS, CP Waveform 2 6.0 6.0 8.0 8.0 ns th(H) th(L) Hold time, high or low Dn to WE, CS, CP Waveform 2 0 0 ns tw (L) WE pulse width, low Waveform 2 7.0 8.0 ns tw (L) CS pulse width, low Waveform 2 6.0 7.0 ns tw (L) CP pulse width, low Waveform 2 7.0 8.0 ns

Philips Semiconductors FAST Products Product specification 74F410Register stack – 16×4 RAM 3-State output register January 8, 1990 5 AC WAVEFORMS Waveform 1. Read cycle timing CP VM VM VM VM VM VM tsu(H) th(H) An VMtw (H) tsu(L) th(L) VMVMQn tw (L) tPLH Waveform 2. Write cycle timing WE VM VMVM VM VMVMCS tsu(H) th(H) tsu(L) th(L) tsu(L) th(L) VM tsu(H) th(H) VM VM VM VM VM tsu(H) t h(H) An, Dn tsu(L) th(L) VM VMVM VM CS WE CP W aveform 3. 3-State output enable time to high level and output disable time from high level VM VM VM tPHZtPZH VOH -0.3V OE Qn Waveform 4. 3-State output enable time to low level and output disable time from low level VM VM VM tPLZtPZL VOL +0.3V Qn OE tPHL NOTES: 1. For all waveforms, VM = 1.5V. 2. The shaded areas indicate when the input is permitted to change for predictable output performance. TEST CIRCUIT AND WAVEFORM tW 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tW AMP (V) tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tW tTLH tTHL 1MHz 500ns 2.5ns 2.5ns Input pulse definition VCC family 74F D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test circuit for 3–state outputs DEFINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value R T = T ermination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude 3.0V 1.5V VM R L 7.0V SWITCH POSITION TEST SWITCH closed openAll other tPLZ , tPZL