74F402PC

74F402 FAIRCHILD | Alldatasheet

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Features

■ Guaranteed 30 MHz data rate ■ Six selectable polynomials ■ Other polynomials available ■ Separate preset and clear controls ■ Expandable ■ Automatic right justification ■ Error output open collector ■ Typical applications: Floppy and other disk storage sys- tems Digital cassette and cartridge systems Data com- munication systems Ordering Code: Logic Symbol Connection Diagram FAST  is a registered trademark of Fairchild Semiconductor Corporation. Ethernet is a registered trademark of Xerox Corporation. Order Number Package Number Package Description 74F402PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2 74F402 Unit Loading/Fan Out Note 1: Open Collector Functional Description The 74F402 Serial Data Polynomial Generator/Checker is an expandable 16-bit programmable device which oper- ates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decod- ing schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream (message polynomial) is divided by a selected poly- nomial. This division results in a remainder (or residue) which is appended to the message as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remain- der. Although it is possible to choose many generating polynomials of a given degree, standards exist that specify a small number of useful polynomials. The 74F402 imple- ments the polynomials listed in Table 1 by applying the appropriate logic levels to the select pins S 0, S1, S2 and S3. The 74F402 consists of a 16-bit register, a Read Only Memory (ROM) and associated control circuitry as shown in the Block Diagram. The polynomial control code pre- sented at inputs S 0, S1, S2 and S3 is decoded by the ROM, selecting the desired polynomial or part of a polynomial by establishing shift mode operation on the register with Exclusive OR (XOR) gates at appropriate inputs. To gener- ate the check bits, the data stream is entered via the Data Inputs (D), using the LOW-to-HIGH transition of the Clock Input (CP). This data is gated with the most significant Register Output (RO) via the Register Feedback Input (RFB), and controls the XOR gates. The Check Word Gen- erate (CWG) must be held HIGH while the data is being entered. After the last data bit is entered, the CWG is brought LOW and the check bits are shifted out of the reg- ister(s) and appended to the data bits (no external gating is needed). To check an incoming message for errors, both the data and check bits are entered through the D Input with the CWG Input held HIGH. The Error Output becomes valid after the last check bit has been entered into the 'F402 by a LOW-to-HIGH transition of CP, with the exception of the Ethernet polynomial (see Applications paragraph). If no detectable errors have occurred during the data transmis- sion, the resultant internal register bits are all LOW and the Error Output (ER ) is HIGH. If a detectable error has occurred, ER is LOW. ER remains valid until the next LOW- to-HIGH transition of CP or until the device has been pre- set or reset. A HIGH on the Master Reset Input (MR) asynchronously clears the entire register. A LOW on the Preset Input (P asynchronously sets the entire register with the exception of: 1. The Ethernet residue selection, in which the registers containing the non-zero residue are cleared; 2. The 56th order polynomial, in which the 8 least signifi- cant register bits of the least significant device are cleared; and, 3. Register S = 0, in which all bits are cleared. Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output IOH /IOL S0–S3 Polynomial Select Inputs 1.0/0.67 20 µA/−0.4 mA CWG Check Word Generate Input 1.0/0.67 20 µA/−0.4 mA D/CW Serial Data/Check Word 285(100)/13.3(6.7) −5.7 mA(−2 mA)/8 mA (4 mA) D Data Input 1.0/0.67 20 µA/−0.4 mA ER Error Output (Note 1) /26.7(13.3) (Note 1) /16 mA (8 mA) RO Register Output 285(100)/13.3(6.7) −5.7 mA(−2 mA)/8 mA (4 mA) CP Clock Pulse 1.0/0.67 20 µA/−0.4 mA SEI Serial Expansion Input 1.0/0.67 20 µA/−0.4 mA RFB Register Feedback 1.0/0.67 20 µA/−0.4 mA MR Master Reset 1.0/0.67 20 µA/−0.4 mA P Preset 1.0/0.67 20 µA/−0.4 mA

3 www.fairchildsemi.com 74F402 TABLE 1. Block Diagram Hex Select Code Polynomial RemarksS3 S2 S1 S0 0LLLL 0 S = 0 CHHL L X 32+X26+X23+X22+X16+ Ethernet DHHLH X 12+X11+X10+X8+X7+X5+X4+X2+X+1 Polynomial EHHHL X 32+X31+X27+X26+X25+X19+X16+ Ethernet FHHHH X 15+X13+X12+X11+X9+X7+X6+X5+X4+X2+X+1 Residue

7 LHHH X 16+X15+X2+1 CRC-16

BHLHH X 16+X12+X5+1 CRC-CCITT 3LLH H X 56+X55+X49+X45+X41+ 2LLHL X 39+X38+X37+X36+X31+ 56th 4LHLL X 22+X19+X17+X16+X15+X14+X12+X11+X9+ Order 8HLLL X 5+X+1 5LHLH X 48+X36+X35+ 9HLLH X 23+X21+ 48th 1LLLH X 15+X13+X8+X2+1O r d e r 6LH HL X 32+X23+X21+ 32nd AHLHL X 11+X2+1O r d e r

www.fairchildsemi.com 4 74F402 TABLE 2.

Applications

In addition to polynomial selection there are four other capabilities provided for in the 74F402 ROM. The first is set or clear selectability. The sixteen internal registers have the capability to be either set or cleared when P is brought LOW. This set or clear capability is done in four groups of 4 (see Table 2, P 0–P3). The second ROM capability (C0) is in determining the polarity of the check word. As is the case with the Ethernet polynomial the check word can be inverted when it is appended to the data stream or as is the case with the other polynomials, the residue is appended with no inversion. Thirdly, the ROM contains a bit (C which is used to select the RFB input instead of the SEI input to be fed into the LSB. This is used when the polyno- mial selected is actually a residue (least significant) stored in the ROM which indicates whether the selected location is a polynomial or a residue. If the latter, then it inhibits the RFB input. As mentioned previously, upon a successful data transmis- sion, the CRC register has a zero residue. There is an exception to this, however, with respect to the Ethernet polynomial. This polynomial, upon a successful data trans- mission, has a non-zero residue in the CRC register (C7 04 DD 7B) 16. In order to provide a no-error indication, two ROM locations have been preloaded with the residue so that by selecting these locations and clocking the device one additional time, after the last check bit has been entered, will result in zeroing the CRC register. In this man- ner a no-error indication is achieved. With the present mix of polynomials, the largest is 56 th order requiring four devices while the smallest is 16th order requiring just one device. In order to accommodate multi- plexing between high order polynomials (X 16th order) and lower order polynomials, a location of all zeros is provided. This allows the user to choose a lower order polynomial even if the system is configured for a higher order one. The 74F402 expandable CRC generator checker contains 6 popular CRC polynomials, 2-16th Order, 2-32nd Order, 1- 48th Order and 1-56th Order. The application diagram shows the 74F402 connected for a 56th Order polynomial. Also shown are the input patterns for other polynomials. When the 74F402 is used with a gated clock, disabling the clock in a HIGH state will ensure no erroneous clocking occurs when the clock is re-enabled. Preset and Master Reset are asynchronous inputs presetting the register to S or clearing to 1s respectively (note Ethernet residue and th Order select code 8, LSB, are exceptions to this). To generate a CRC, the pattern for the selected polynomial is applied to the S inputs, the register is preset or cleared as required, clock is enabled, CWG is set HIGH, data is applied to D input, output data is on D/CW. When the last data bit has been entered, CWG is set LOW and the regis- ter is clocked for n bits (where n is the order of the polyno- mial). The clock may now be stopped if desired (holding CWG LOW and clocking the register will output zeros from D/CW after the residue has been shifted out). To check a CRC, the pattern for the selected polynomial is applied to the S inputs, the register is preset or cleared as required, clock is enabled, CWG is set HIGH, the data stream including the CRC is applied to D input. When the last bit of the CRC has been entered, the ER output is checked: HIGH = error free data, LOW = corrupt data. The clock may now be stopped if desired. To implement polynomials of lower order than 56th, select the number of packages required for the order of polyno- mial and apply the pattern for the selected polynomial to the S inputs (0000 on S inputs disables the package from the feedback chain). Select Code P

3 P2 P1 P0 C 2 C 1 C 0 Polynomial

0 0000100 S = 0 C 1111101 E t h e r n e t D 1111101 P o l y n o m i a l E 0000000 E t h e r n e t F 0000010 R e s i d u e 7 1111100 CRC-16 B 1111100 CRC-CCITT 3 1111100 2 1111100 5 6 t h 4 1111100 O r d e r 8 0011100 5 1111100 4 8 t h 9 1111100 O r d e r 1 1111100 6 1111100 3 2 n d A 1111100 O r d e r

5 www.fairchildsemi.com 74F402

www.fairchildsemi.com 6 74F402 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.4 VM i n IOH = −5.7 mA (RO, D/CW) Voltage 5% V CC 2.7 I OH = −5.7 mA (RO, D/CW) VOL Output LOW 10% V CC 0.5 IOL = 16 mA (ER) Voltage 10% V CC 0.5 I OL = 8 mA (D/CW, RO) IIH Input HIGH 5.0 µAM a x V IN = 2.7V Current IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V Breakdown Test ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.4 mA Max V IN = 0.5V IOS Output Short-Circuit Current −20 −130 mA Max V OUT = 0V (D/CW, RO) IOHC Open Collector, Output 250 µAM i n VOUT = VCC (ER)OFF Leakage Test ICC Power Supply Current 110 165 mA Max

7 www.fairchildsemi.com 74F402 Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF C L = 50 pF Min Typ Max Min Max Min Max fMAX Maximum Clock Frequency 30 45 30 30 MHz ns ns ns tPLH Propagation Delay P to RO tPLH Propagation Delay P to ER ns tPHL Propagation Delay MR to RO tPLH Propagation Delay MR to ER ns ns ns

www.fairchildsemi.com 8 74F402 AC Operating Requirements Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V V CC = +5.0V Min Max Min Max Min Max tS(H) Setup Time, HIGH or LOW 4.5 6.0 5.0 ns tS(L) SEI to CP 4.5 6.0 5.0 tH (H) Hold Time, HIGH or LOW 0 1.0 0 tH (L) SEI to CP 0 1.0 0 tS(H) Setup Time, HIGH or LOW 11.0 14.0 12.5 ns tS(L) RFB to CP 11.0 14.0 12.5 tH (H) Hold Time, HIGH or LOW 0 0 0 tH (L) RFB to CP 0 0 0 tS(H) Setup Time, HIGH or LOW 13.5 16.0 15.0 ns tS(L) S 1 to CP 13.0 15.5 14.5 tH (H) Hold Time, HIGH or LOW 0 0 0 tH (L) S 1 to CP 0 0 0 tS(H) Setup Time, HIGH or LOW 9.0 11.5 10.0 ns tS(L) D to CP 9.0 11.5 10.0 tH (H) Hold Time, HIGH or LOW 0 0 0 tH (L) D to CP 0 0 0 tS(H) Setup Time, HIGH or LOW 7.0 9.0 8.0 ns tS(L) CWG to CP 5.5 8.0 6.5 tH (H) Hold Time, HIGH or LOW 0 0 0 tH (L) CWG to CP 0 0 0 tW (H) Clock Pulse Width 4.0 7.0 4.5 ns tW (L) HIGH or LOW 4.0 5.0 4.5 tW (H) MR Pulse Width, HIGH 4.0 7.0 4.5 ns tW (L) P Pulse Width, LOW 4.0 5.0 4.5 ns tREC Recovery Time 3.0 4.0 3.5 ns MR to CP tREC Recovery Time 5.0 6.5 6.0 P to CP

9 www.fairchildsemi.com 74F402 Serial Data Polynomial Generator/Checker Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com