74F402

54F402DM NSC | Alldatasheet

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Technical content

Features

Y Guaranteed 30 MHz data rate Y Six selectable polynomials Y Other polynomials available Y Separate preset and clear controls Y Expandable Y Automatic right justification Y Error output open collector Y Typical applications: Floppy and other disk storage systems Digital cassette and cartridge systems Data communication systems Commercial Military Package Package DescriptionNumber 74F402PC N16E 16-Lead (0.300 × Wide) Molded Dual-In-Line 54F402DM (Note 1) J16A 16-Lead Ceramic Dual-In-Line 54F402FM (Note 1) W16A 16-Lead Cerpack 54F402LM (Note 1) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbol Connection Diagrams TL/F/9535–4 Pin Assignment for DIP, SOIC and Flatpak TL/F/9535–1 Pin Assignment for LCC TL/F/9535–2 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. EthernetÉ is a registered trademark of Xerox Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH/IOL S0 –S3 Polynomial Select Inputs 1.0/0.67 20 mA/b0.4 mA CWG Check Word Generate Input 1.0/0.67 20 mA/b0.4 mA D/CW Serial Data/Check Word 285(100)/13.3(6.7) b5.7 mA( b2 mA)/8 mA (4 mA) D Data Input 1.0/0.67 20 mA/b0.4 mA ER Error Output */26.7(13.3) */16 mA (8 mA) RO Register Output 285(100)/13.3(6.7) b5.7 mA( b2 mA)/8 mA (4 mA) CP Clock Pulse 1.0/0.67 20 mA/b0.4 mA SEI Serial Expansion Input 1.0/0.67 20 mA/b0.4 mA RFB Register Feedback 1.0/0.67 20 mA/b0.4 mA MR Master Reset 1.0/0.67 20 mA/b0.4 mA P Preset 1.0/0.67 20 mA/b0.4 mA *Open Collector Functional Description The ’F402 Serial Data Polynomial Generator/Checker is an expandable 16-bit programmable device which operates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decoding schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream (message polynomial) is divided by a selected polynomial. This divi- sion results in a remainder (or residue) which is appended to the message as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remainder. Although it is possi- ble to choose many generating polynomials of a given de- gree, standards exist that specify a small number of useful polynomials. The ’F402 implements the polynomials listed in Table I by applying the appropriate logic levels to the select pins S 0,S 1,S 2 and S 3. The ’F402 consists of a 16-bit register, a Read Only Memory (ROM) and associated control circuitry as shown in the Block Diagram. The polynomial control code presented at inputs S 0,S 1,S 2 and S 3 is decoded by the ROM, selecting the desired polynomial or part of a polynomial by establish- ing shift mode operation on the register with Exclusive OR (XOR) gates at appropriate inputs. To generate the check bits, the data stream is entered via the Data Inputs (D), us- ing the LOW-to-HIGH transition of the Clock Input (CP). This data is gated with the most significant Register Output (RO) via the Register Feedback Input (RFB), and controls the XOR gates. The Check Word Generate (CWG) must be held HIGH while the data is being entered. After the last data bit is entered, the CWG is brought LOW and the check bits are shifted out of the register(s) and appended to the data bits (no external gating is needed). To check an incoming message for errors, both the data and check bits are entered through the D Input with the CWG Input held HIGH. The Error Output becomes valid af- ter the last check bit has been entered into the ’F402 by a LOW-to-HIGH transition of CP, with the exception of the Ethernet polynomial (see Applications paragraph). If no de- tectable errors have occurred during the data transmission, the resultant internal register bits are all LOW and the Error Output (ER ) is HIGH. If a detectable error has occurred, ER is LOW. ER remains valid until the next LOW-to-HIGH tran- sition of CP or until the device has been preset or reset. A HIGH on the Master Reset Input (MR) asynchronously clears the entire register. A LOW on the Preset Input (P ) asynchronously sets the entire register with the exception of:

1 The Ethernet residue selection, in which the registers

containing the non-zero residue are cleared;

2 The 56th order polynomial, in which the 8 least significant

register bits of the least significant device are cleared; and,

3 Register S

e0, in which all bits are cleared.

Hex Select Code Polynomial RemarksS3 S2 S1 S0

0 LLLL 0 S e0

CH H L L X 32aX26aX23aX22aX16a Ethernet D HHLH X 12aX11aX10aX8aX7aX5aX4aX2aXa1 Polynomial E HHHL X 32aX31aX27aX26aX25aX19aX16a Ethernet F HHHH X 15aX13aX12aX11aX9aX7aX6aX5aX4aX2aXa1 Residue

7 LHHH X 16aX15aX2a1 CRC-16

B HLHH X 16aX12aX5a1 CRC-CCITT 3L L H H X 56aX55aX49aX45aX41a

2 LLHL X 39aX38aX37aX36aX31a 56th

4 LHLL X 22aX19aX17aX16aX15aX14aX12aX11aX9a Order

8 HLLL X 5aXa1

5 LHLH X 48aX36aX35a

1 LLLH X 15aX13aX8aX2a1

6L H H L X 32aX23aX21a 32nd A HLHL X 11aX2a1 Order Block Diagram TL/F/9535–5

Select Code P 3 P2 P1 P0 C2 C1 C0 Polynomial 0 0000100 S e0 C 1 1 1 1 1 0 1 Ethernet D 1 1 1 1 1 0 1 Polynomial E 0 0 0 0 0 0 0 Ethernet F 0 0 0 0 0 1 0 Residue 7 1 1 1 1 1 0 0 CRC-16 B 1 1 1 1 1 0 0 CRC-CCITT 3 1111100 2 1 1 1 1 1 0 0 56th 4 1 1 1 1 1 0 0 Order 8 0011100 5 1111100 48th9 1111100 Order1 1111100 6 1 1 1 1 1 0 0 32nd A 1 1 1 1 1 0 0 Order

Applications

In addition to polynomial selection there are four other ca- pabilities provided for in the ’F402 ROM. The first is set or clear selectability. The sixteen internal registers have the capability to be either set or cleared when P is brought LOW. This set or clear capability is done in four groups of 4 (see Table II, P 0 –P3). The second ROM capability (C 0)i si n determining the polarity of the check word. As is the case with the Ethernet polynomial the check word can be invert- ed when it is appended to the data stream or as is the case with the other polynomials, the residue is appended with no inversion. Thirdly, the ROM contains a bit (C 1) which is used to select the RFB input instead of the SEI input to be fed into the LSB. This is used when the polynomial selected is actually a residue (least significant) stored in the ROM which indicates whether the selected location is a polynomi- al or a residue. If the latter, then it inhibits the RFB input. As mentioned previously, upon a successful data transmis- sion, the CRC register has a zero residue. There is an ex- ception to this, however, with respect to the Ethernet poly- nomial. This polynomial, upon a successful data transmis- sion, has a non-zero residue in the CRC register (C7 04 DD 7B) 16. In order to provide a no-error indication, two ROM locations have been preloaded with the residue so that by selecting these locations and clocking the device one addi- tional time, after the last check bit has been entered, will result in zeroing the CRC register. In this manner a no-error indication is achieved. With the present mix of polynomials, the largest is 56 th or- der requiring four devices while the smallest is 16 th order requiring just one device. In order to accommodate multi- plexing between high order polynomials (X 16 th order) and lower order polynomials, a location of all zeros is provided. This allows the user to choose a lower order polynomial even if the system is configured for a higher order one. The ’F402 expandable CRC generator checker contains 6 popular CRC polynomials, 2-16 th Order, 2-32 nd Order, 1- 48th Order and 1-56 th Order. The application diagram shows the ’F402 connected for a 56 th Order polynomial. Also shown are the input patterns for other polynomials. When the ’F402 is used with a gated clock, disabling the clock in a HIGH state will ensure no erroneous clocking occurs when the clock is re-enabled. Preset and Master Re- set are asynchronous inputs presetting the register to S or clearing to 1s respectively (note Ethernet residue and 56 th Order select code 8, LSB, are exceptions to this). To generate a CRC, the pattern for the selected polynomial is applied to the S inputs, the register is preset or cleared as required, clock is enabled, CWG is set HIGH, data is applied to D input, output data is on D/CW. When the last data bit has been entered, CWG is set LOW and the register is clocked for n bits (where n is the order of the polynomial). The clock may now be stopped if desired (holding CWG LOW and clocking the register will output zeros from D/CW after the residue has been shifted out). To check a CRC, the pattern for the selected polynomial is applied to the S inputs, the register is preset or cleared as required, clock is enabled, CWG is set HIGH, the data stream including the CRC is applied to D input. When the last bit of the CRC has been entered, the ER output is checked: HIGH eerror free data, LOW ecorrupt data. The clock may now be stopped if desired. To implement polynomials of lower order than 56 th, select the number of packages required for the order of polynomial and apply the pattern for the selected polynomial to the S inputs (0000 on S inputs disables the package from the feedback chain).

Applications (Continued) TL/F/9535–6

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C Ambient Temperature under Bias b55§Ct o a125§C Junction Temperature under Bias b55§Ct o a175§C Plastic b55§Ct o a150§C VCC Pin Potential to Ground Pin b0.5V to a7.0V Input Voltage (Note 2) b0.5V to a7.0V Input Current (Note 2) b30 mA to a5.0 mA Voltage Applied to Output in HIGH State (with V CC e 0V) Standard Output b0.5V to V CC TRI-STATEÉ Output b0.5V to a5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Recommended Operating Conditions Free Air Ambient Temperature Military b55§Ct o a125§C Commercial 0 §Ct o a70§C Supply Voltage Military a4.5V to a5.5V Commercial a4.5V to a5.5V Symbol Parameter 54F/74F Units V CC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage b1.2 V Min I IN eb 18 mA VOH Output HIGH 54F 10% V CC 2.4 I OH eb 2 mA (RO, D/CW) Voltage 74F 10% V CC 2.4 V Min I OH eb 5.7 mA (RO, D/CW) 74F 5% V CC 2.7 I OH eb 5.7 mA (RO, D/CW) VOL Output LOW 54F 10% V CC 0.4 I OL e 4 mA (D/CW, RO) Voltage 54F 10% V CC 0.4 V Min IOL e 8m A( E R ) 74F 10% V CC 0.5 I OL e 16 mA (ER ) 74F 10% V CC 0.5 I OL e 8 mA (D/CW, RO) IIH Input HIGH Current 54F 20.0 mA Max VIN e 2.7V 74F 5.0 IBVI Input HIGH Current 54F 100 mA Max VIN e 7.0V Breakdown Test 74F 7.0 ICEX Output HIGH 54F 250 mA Max VOUT e VCC Leakage Current 74F 50 VID Input Leakage 74F 4.75 V 0.0 IID e 1.9 mA Test All Other Pins Grounded IOD Output Leakage 74F 3.75 mA 0.0 VIOD e 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current b0.4 mA Max V IN e 0.5V IOS Output Short-Circuit Current b20 b130 mA Max V OUT e 0V (D/CW, RO) IOHC Open Collector, Output 250 mA Min VOUT e VCC (ER) OFF Leakage Test ICC Power Supply Current 110 165 mA Max

TA ea 25§C TA,V CC e Mil T A,V CC e ComSymbol Parameter V CC ea 5.0V CL e 50 pF C L e 50 pF Units CL e 50 pF Min Typ Max Min Max Min Max fmax Maximum Clock Frequency 30 45 30 30 MHz

Symbol Parameter TA ea 25§C TA,V CC e Mil T A,V CC e Com UnitsVCC ea 5.0V Min Max Min Max Min Max ts(H) Setup Time, HIGH or LOW 4.5 6.0 5.0 ts(L) SEI to CP 4.5 6.0 5.0 th(H) Hold Time, HIGH or LOW 0 1.0 0 ns th(L) SEI to CP 0 1.0 0 ts(H) Setup Time, HIGH or LOW 11.0 14.0 12.5 ts(L) RFB to CP 11.0 14.0 12.5 th(H) Hold Time, HIGH or LOW 0 0 0 ns th(L) RFB to CP 0 0 0 ts(H) Setup Time, HIGH or LOW 13.5 16.0 15.0 ts(L) S 1 to CP 13.0 15.5 14.5 th(H) Hold Time, HIGH or LOW 0 0 0 ns th(L) S 1 to CP 0 0 0 ts(H) Setup Time, HIGH or LOW 9.0 11.5 10.0 ts(L) D to CP 9.0 11.5 10.0 th(H) Hold Time, HIGH or LOW 0 0 0 ns th( L ) Dt oC P 0 0 0 ts(H) Setup Time, HIGH or LOW 7.0 9.0 8.0 ts(L) CWG to CP 5.5 8.0 6.5 th(H) Hold Time, HIGH or LOW 0 0 0 ns th(L) CWG to CP 0 0 0 tw(H) MR Pulse Width, HIGH 4.0 7.0 4.5 ns tw(L) P Pulse Width, LOW 4.0 5.0 4.5 ns trec Recovery Time 3.0 4.0 3.5MR to CP trec Recovery Time 5.0 6.5 6.0 ns P to CP

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 402 P C Temperature Range Family Special Variations 74FeCommercial QB e Military grade device with 54FeMilitary environmental and burn-in processingDevice Type Temperature RangePackage Code CeCommercial (0 §Ct o a70§C)P e Plastic DIP MeMilitary ( b55§Ct o a125§C)D e Ceramic DIP F e Flatpak L e Leadless Chip Carrier (LCC)

Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L) 16-Lead Ceramic Dual-In-Line Package (D)

Physical Dimensions inches (millimeters) (Continued) 16-Lead (0.300 × Wide) Molded Plastic Dual-In-Line Package (P)

54F/74F402 Serial Data Polynomial Generator/Checker Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flatpak (F) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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