74F401

74F401 FAIRCHILD | Alldatasheet

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■ Eight selectable polynomials ■ Error indicator ■ Separate preset and clear controls ■ Automatic right justification ■ Fully compatible with all TTL logic families ■ 14-pin package ■ 9401 equivalent ■ Typical applications: Floppy and other disk storage systems Digital cassette and cartridge systems Data communication systems Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Order Number Package Number Package Description 74F401SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F401PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2 74F401 Unit Loading/Fan Out Functional Description The 74F401 is a 16-bit programmable device which oper- ates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decod- ing schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream (message polynomial) is divided by a selected poly- nomial. This division results in a remainder which is appended to the message as check bits. For error check- ing, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remainder. Although it is possible to choose many generating polyno- mials of a given degree, standards exist that specify a small number of useful polynomials. The 74F401 imple- ments the polynomials listed in Table 1 by applying the appropriate logic levels to the select pins S 0, S1 and S2. The 74F401 consists of a 16-bit register, a Read Only Memory (ROM) and associated control circuitry as shown in the block diagram. The polynomial control code pre- sented at inputs S 0, S1 and S2 is decoded by the ROM, selecting the desired polynomial by establishing shift mode operation on the register with Exclusive OR gates at appro- priate inputs. To generate the check bits, the data stream is entered via the Data inputs (D), using the HIGH-to-LOW transition of the Clock input (CP). This data is gated with the most significant output (Q) of the register, and controls the Exclusive OR gates Figure 1. The Check Word Enable (CWE) must be held HIGH while the data is being entered. After the last data bit is entered, the CWE is brought LOW and the check bits are shifted out of the register and appended to the data bits using external gating Figure 2. To check an incoming message for errors, both the data and check bits are entered through the D input with the CWE input held HIGH. The 74F401 is not in the data path, but only monitors the message. The Error Output becomes valid after the last check bit has been entered into the 74F401 by a HIGH-to-LOW transition of CP . If no detect- able errors have occurred during the data transmission, the resultant internal register bits are all LOW and the Error Output (ER) is LOW. If a detectable error has occurred, ER is HIGH. A HIGH on the Master Reset input (MR) asynchronously clears the register. A LOW on the Preset input (P ) asyn- chronously sets the entire register if the control code inputs specify a 16-bit polynomial; in the case of 12- or 8-bit check polynomials only the most significant 12 or 8 register bits are set and the remaining bits are cleared. TABLE 1. Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output IOH /IOL S0–S2 Polynomial Select Inputs 1.0/1.0 20 µA/−0.6 mA D Data Input 1.0/1.0 20 µA/−0.6 mA CP Clock Input (Operates on HIGH-to-LOW Transition) 1.0/1.0 20 µA/−0.6 mA CWE Check Word Enable Input 1.0/1.0 20 µA/−0.6 mA P Preset (Active LOW) Input 1.0/1.0 20 µA/−0.6 mA MR Master Reset (Active HIGH) Input 1.0/1.0 20 µA/−0.6 mA Q Data Output 50/33.3 −1 mA/20 mA ER Error Output 50/33.3 −1 mA/20 mA Select Code Polynomial RemarksS2 S1 S0 LLL X 16 + X15 + X2 + 1 CRC-16 LLH X 16 + X14 + X + 1 CRC-16 REVERSE LHL X 16 + X15 + X13 + X7 + X4 + X2 + X1 + 1 LHH X 12 + X11 + X3 + X2 + X + 1 CRC-12 HLL X 8 + X7 + X5 + X4 + X + 1 HLH X 8 + 1 LRC-8 HHL X 16 + X12 + X5 + 1 CRC-CCITT HHH X 16 + X11 + X4 + 1 CRC-CCITT REVERSE

www.fairchildsemi.com 4 74F401 Absolute Maximum Ratings(Note 4) Recommended Operating Conditions Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 5: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 5) −0.5V to +7.0V Input Current (Note 5) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.5 VM i n IOH = −1 mA Voltage 5% V CC 2.7 I OH = −1 mA VOL Output LOW 10% V CC 0.5 V Min I OL = 20 mA Voltage IIH Input HIGH Current 5.0 µAM a x V IN = 2.7V IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V Breakdown Test ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V ICCH Power Supply Current 70 105 mA Max V O = HIGH

5 www.fairchildsemi.com 74F401 AC Operating Requirements Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max fMAX Maximum Clock Frequency 100 85 MHz tPLH Propagation Delay 4.5 11.5 4.5 13.5 nstPHL CP to Q 4.0 10.0 4.0 11.0 tPHL Propagation Delay 3.0 7.5 3.0 8.0 ns MR to Q tPLH Propagation Delay 3.0 8.5 3.0 9.5 ns P to Q tPHL Propagation Delay 3.5 11.0 3.5 12.0 ns MR to ER tPLH Propagation Delay 3.0 8.5 3.0 10.0 ns P to ER tPLH Propagation Delay 5.0 13.0 5.0 14.5 nstPHL CP to ER 4.5 11.5 4.5 12.5 Symbol Parameter TA = +25°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V M i nM a xM i nM a x tS(H) Set-up Time, HIGH or LOW 5.0 5.5 tS(L) D to CP 5.0 5.5 tS(H) Set-up Time, HIGH or LOW 4.0 4.5 nstS(L) CWE to CP 4.0 4.5 tH (H) Hold Time, HIGH or LOW 2.0 2.0 tH (L) D and CWE to CP 2.0 2.0 tW (L) P Pulse Width, LOW 7.0 8.0 ns tW (H) Clock Pulse Width, 5.0 6.0 ns tW (L) HIGH or LOW 5.0 6.0 tW (H) MR Pulse Width, HIGH 5.0 5.5 ns tREC Recovery Time 4.0 4.5 ns MR to CP tREC Recovery Time 2.0 2.0 ns P to CP

www.fairchildsemi.com 6 74F401 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

7 www.fairchildsemi.com 74F401 CRC Generator/Checker Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com