74F385 PHILIPS | Alldatasheet

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Technical content

Philips Semiconductors Product specification 74F385Quad serial adder/subtractor

11989 Sep 20 853–0868 97678

FEATURES

  • Four independent adders/subtractors
  • Two’s complement arithmetic
  • Synchronous operation
  • Common Clear and Clock
  • 74F385 is designed for use with serial multipliers in implementing digital filters and butterfly networks in fast Fourier transforms

DESCRIPTION

The 74F385 contains four independent adder/subtractor elements with common Clock and Master Reset. Each adder/subtractor contains a sum flop-flop and a carry flip-flop for synchronous operations. Flip-flop state changes occur on the rising edge of the Clock Pulse (CP) input signal. The Select (S) input should be Low for the Add (A plus B) mode and High for the Subtract (A minus B) mode. A Low signal on the asynchronous Master Reset (MR) input clears the sum flip-flop and resets the Carry flip-flop to zero in the Add mode or presets it to one in the Subtract mode. PIN CONFIGURA TION 147 138 VCCCP GND MR SF00928 129 1110 TYPE TYPICAL fMAX TYPICAL SUPPL Y CURRENT (TOTAL) 74F385 140 MHz 55mA

ORDERING INFORMATION

DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 20-pin plastic DIP N74F385N 20-pin plastic SO N74F385D INPUT AND OUTPUT LOADING AND F AN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW A0 – A3 A operand inputs 1.0/1.0 20µA/0.6mA B0 – B3 B operand inputs 1.0/1.0 20µA/0.6mA S0 – S3 Function select inputs 1.0/1.0 20µA/0.6mA CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.6mA MR Asynchronous Master Reset input (active Low) 1.0/1.0 20µA/0.6mA F0–F3 Sum or difference outputs 50/33 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

Philips Semiconductors Product specification 74F385Quad serial adder/subtractor

1989 Sep 20 2

VCC = Pin 20 GND = Pin 10 A0 B0 A1 B1 A2 B2 A3 B3 5 4 6 7 15 14 16 17 CP MR 2 9 12 19 SF00929 IEC/IEEE SYMBOL 5 P SF00930 Q 4(3CI/ 3BI) 3C O/ 3BO /P–Q R FUNCTION TABLE INPUTS CARRY FLIP-FLOP STATE OUTPUTS OPERATING MODEMR S A B Before↑ After↑ F MODE L L X X L L L ClearL H X X H H L Clear H L L L L L L Add H L L L H L H Add H L L H L L H AddH L L H H H L AddH L H L L L H Add H L H L H H L H L H H L H L H L H H H H H H H L L L L H Subtract H H L L H H L Subtract H H L H L L L SubtractH H L H H L H SubtractH H H L L H L Subtract H H H L H H H H H H H L L H H H H H H H L H = High voltage level L = Low voltage level X = Don’t care ↑ = Low-to-High Clock transition

Philips Semiconductors Product specification 74F385Quad serial adder/subtractor

1989 Sep 20 3

VCC = Pin 20 GND = Pin 10 SF00931 MR CP R D CP Q SUM D CP S R Q F02 R D CP Q SUM D CP S R Q F19 R D CP Q SUM D CP S R Q F212 R D CP Q SUM D CP S R Q F319 CARRY CARRY CARRY CARRY

Philips Semiconductors Product specification 74F385Quad serial adder/subtractor

1989 Sep 20 4

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 40 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature –65 to +150 °C RECOMMENDED OPERA TING CONDITIONS SYMBOL PARMETER LIMITS UNITSYMBOL PARMETER MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range 0 70 °C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST LIMITS UNIT SYMBOL PARAMETER CONDITIONS 1 MIN TYP 2 MAX VOH High-level output voltage VCC = MIN, VIL = MAX, ±10%V CC 2.5 V VOH High-level output voltage VIH = MIN, IOH = MAX ±5%V CC 2.7 3.4 V VOL Low-level output voltage VCC = MIN, VIL = MAX, ±10%V CC 0.35 0.50 V VOL Low-level output voltage VIH = MIN, IOL = MAX ±5%V CC 0.35 0.50 V VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V II Input current at maximum input voltage VCC = MAX, VI = 7.0V 100 µA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current VCC = MAX, VI = 0.5V –20 µA IOS Short-circuit output current3 VCC = MAX –60 –150 mA ICC Supply current (total) VCC = MAX 55 80 mA Notes: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.

Philips Semiconductors Product specification 74F385Quad serial adder/subtractor

1989 Sep 20 5

AC ELECTRICAL CHARACTERISTICS LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX fMAX Maximum clock frequency W aveform 1 105 140 90 MHz tPLH tPHL Propagation delay, Cn to Fn W aveform 1 3.0 3.5 5.0 5.5 8.0 9.0 2.5 3.5 9.0 10.0 ns AC SETUP REQUIREMENTS LIMITS Tamb = +25°C Tamb = 0°C to +70°C SYMBOL PARAMETER TEST VCC = +5.0V VCC = +5.0V ± 10% UNIT CONDITION C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX ts (H) ts (L) Setup time, High or Low An, Bn or Sn to CP W aveform 3 12.0 12.0 12.0 12.0 ns th (H) th (L) Hold time, High or Low An, Bn or Sn to CP W aveform 3 0 0 ns ts (H) ts (L) CP Pulse width High or Low W aveform 2 6.0 6.0 6.0 6.0 ns tw (L) MR Pulse width Low W aveform 2 6.0 6.0 ns tREC (L) Recovery time MR to CP W aveform 2 8.5 9.5 ns AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performances. CP VM VMVM tw (H) 1/fmax VMVM tPLHtw (L)tPHL Fn SF00932 W aveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency VM VM VMVM Fn MR tPHL tREC SF00933 CP tW (L) Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time VM VM VM VM VM VM ts(L) t h(L)ts(H) t h(H) An, Bn, Sn CP SF00934 Waveform 3. Data and Select Setup and Hold Times

Philips Semiconductors Product specification 74F385Quad serial adder/subtractor

1989 Sep 20 6

TEST CIRCUIT AND W AVEFORM tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns Input Pulse Definition VCC family 74F D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test Circuit for Totem-Pole Outputs DEFINITIONS: R L = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. R T = T ermination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude 3.0V 1.5V VM SF00006