74F382

74F382 FAIRCHILD | Alldatasheet

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Technical content

Features

■ Performs six arithmetic and logic functions ■ Selectable LOW (clear) and HIGH (preset) functions ■ LOW input loading minimizes drive requirements ■ Carry output for ripple expansion ■ Overflow output for twos complement arithmetic Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F382SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F382SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F382PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

3 www.fairchildsemi.com 74F382 Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Inputs Outputs Function S0 S1 S2 C n A n B n F0 F1 F2 F3 OVR C n + 4 C L E A R LLLLXXLLLL H H HXXLLLL H H B M I N U S AHLLLLLH H H HL L LLHLH H HL H LHLLLLL L L LHHHHHH L L HLLLLLL L H HLHHHHH L H HHLHL L L L L HHHL L L L L H A MINUS B L H L L L L H H H H L L LLHLLLL L L LHLLHHH L H LHHHHHH L L HLLLLLL L H HLHHLLL L L HHLHHHH L H HHHL L L L L H A P L U S B H HLLLLLLLL L L L LHHHHH L L LHLHHHH L L LHHLHHH L H HLLHLLL L L HLHLLLL L H H HLLLLL L H HHHHHHH L H A ⊕ B LLH XLLLLLL L L XLHHHHH L L LHLHHHH L L X H HLLLL H H HHLHHHH H H A + B HLH XLLLLLL L L XLHHHHH L L XHLHHHH L L LHHHHHH L L HHHHHHH H H A B LH H XLLLLLL H H XLHLLLL L L X HLLLLL H H LHHHHHH L L HHHHHHH H H PRESET H H H X L L H H H H L L XLHHHHH L L XHLHHHH L L LHHHHHH L L HHHHHHH H H

www.fairchildsemi.com 4 74F382 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

5 www.fairchildsemi.com 74F382 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.5 VM i n IOH = −1 mA Voltage 5% V CC 2.7 I OH = −1 mA VOL Output LOW 10% V CC 0.5 V Min I OL = 20 mA Voltage IIH Input HIGH 5.0 µAM a x V IN = 2.7V Current IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V Breakdown Test ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 V IN = 0.5V (S0 – S2) −2.4 mA Max V IN = 0.5V (A0 – A3, B0 – B3) −3.0 V IN = 0.5V (Cn) IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V ICC Power Supply Current 54 81 mA Max

www.fairchildsemi.com 6 74F382 Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max ns ns ns ns ns ns ns ns

7 www.fairchildsemi.com 74F382 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D

www.fairchildsemi.com 8 74F382 4-Bit Arithmetic Logic Unit Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com