74F378 FAIRCHILD | Alldatasheet

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■ 6-bit high-speed parallel register ■ Positive edge-triggered D-type inputs ■ Fully buffered common clock and enable inputs ■ Input clamp diodes limit high-speed termination effects ■ Full TTL and CMOS compatible Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F378SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F378SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F378PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2 74F378 Unit Loading/Fan Out Functional Description The 74F378 consists of six edge-triggered D-type flip-flops with individual D inputs and Q inputs. The Clock (CP) and Enable (E ) inputs are common to all flip-flops. When the E input is LOW, new data is entered into the reg- ister on the LOW-to-HIGH transition of the CP input. When the E input is HIGH the register will retain the present data independent of the CP input. Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial /c17 = LOW-to-HIGH Clock Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL E Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA D 0–D 5 Data Inputs 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA Q 0–Q 5 Outputs 50/33.3 −1 mA/20 mA Inputs Output E CP D n Q n H /c17 X No Change L /c17 HH L /c17 LL

3 www.fairchildsemi.com 74F378 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.5 VM i n IOH = −1 mA Voltage 5% V CC 2.7 I OH = −1 mA VOL Output LOW 10% V CC 0.5 V Min I OL = 20 mA Voltage IIH Input HIGH 5.0 µAM a x V IN = 2.7V Current IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V Breakdown Test ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V ICCL Power Supply Current 30 45 mA Max V O = LOW

www.fairchildsemi.com 4 74F378 AC Operating Requirements Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF C L = 50 pF Min Typ Max Min Max Min Max fMAX Maximum Input Frequency 80 100 70 80 MHz ns Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V V CC = +5.0V Min Max Min Max Min Max tS(H) Setup Time, HIGH or LOW 4.0 5.0 4.0 ns tS(L) D n to CP 4.0 5.0 4.0 tH (H) Hold Time, HIGH or LOW 0 2.0 0 tH (L) D n to CP 0 2.0 0 tS(H) Setup Time, HIGH or LOW 6.0 4.5 6.0 ns tS(L) E to CP 10.0 13.0 10.0 tH (H) Hold Time, HIGH or LOW 0 0 0 tH (L) E to CP 000 tW (H) CP Pulse Width 4.0 5.0 4.0 ns tW (L) HIGH or LOW 6.0 7.5 6.0

5 www.fairchildsemi.com 74F378 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

www.fairchildsemi.com 6 74F378 Parallel D-Type Register with Enable Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com