74F377 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

■ Ideal for addressable register applications ■ Clock enable for address and data synchronization

applications

■ Eight edge-triggered D-type flip-flops ■ Buffered common clock ■ See 74F273 for master reset version ■ See 74F373 for transparent latch version ■ See 74F374 for 3-STATE version Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F377SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F377SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F377PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2 74F377 Unit Loading/Fan Out Mode Select-Function Table H = HIGH Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition L = LOW Voltage Level I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition X = Immaterial /c17 = LOW-to-HIGH Clock Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL D 0–D 7 Data Inputs 1.0/1.0 20 µA/−0.6 mA CE Clock Enable (Active LOW) 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input 1.0/1.0 20 µA/−0.6 mA Q 0–Q 7 Data Outputs 50/33.3 −1 mA/20 mA Operating Mode Inputs Output CP CE D n Q n Load “1” /c17 Ih H Load “0” /c17 II L Hold /c17 h X No Change (Do Nothing) X H X No Change

3 www.fairchildsemi.com 74F377 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.5 VM i n IOH = −1 mA Voltage 5% V CC 2.7 I OH = −1 mA VOL Output LOW 10% V CC 0.5 V Min I OL = 20 mA Voltage IIH Input HIGH Current 5.0 µAM a x V IN = 2.7V IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V Breakdown Test IIL Input LOW Current −0.6 mA Max V IN = 0.5V IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V ICEX Output HIGH Leakage Current 50 µAM a x V OUT = VCC VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded ICCH Power Supply Current 35 46 mA Max CP = /c17 ICCL 44 56 D n = MR = HIGH

www.fairchildsemi.com 4 74F377 AC Operating Requirements Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF C L = 50 pF Min Typ Max Min Max Min Max fMAX Maximum Clock Frequency 130 85 105 MHz ns Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V V CC = +5.0V Min Max Min Max Min Max tS(H) Setup Time, HIGH or LOW 3.0 3.5 3.0 ns tS(L) D n to CP 3.5 4.0 3.5 tH (H) Hold Time, HIGH or LOW 0.5 1.0 0.5 ns tH (L) D n to CP 1.0 1.0 1.0 tS(H) Setup Time, HIGH or LOW 4.1 4.0 4.1 nstS(L) CE to CP 3.5 5.0 4.0 tH (H) Hold Time, HIGH to LOW 0.5 1.5 0.5 nstH (L) CE to CP 2.0 2.5 2.0 tW (H) Clock Pulse Width, 6.0 5.0 6.0 ns tW (L) HIGH or LOW 6.0 5.0 6.0

5 www.fairchildsemi.com 74F377 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D

www.fairchildsemi.com 6 74F377 Octal D-Type Flip-Flop with Clock Enable Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com