74F374 FAIRCHILD | Alldatasheet

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■ Edge-triggered D-type inputs ■ Buffered positive edge-triggered clock ■ 3-STATE outputs for bus-oriented applications ■ Guaranteed 4000V minimum ESD protection Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F374SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F374MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74F374PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2 74F374 Unit Loading/Fan Out Functional Description The 74F374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE ) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Opera- tion of the OE input does not affected the state of the flip- flops. Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance /c17 = LOW-to-HIGH Clock Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL D 0–D 7 Data Inputs 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA OE 3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA O 0–O 7 3-STATE Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) Inputs Internal Output D n CP OE Register O n H /c17 LH H L /c17 LL L XXH X Z

3 www.fairchildsemi.com 74F374 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.5 VM i n IOH = −1 mA Voltage 10% V CC 2.4 I OH = −3 mA 5% VCC 2.7 I OH = −1 mA 5% VCC 2.7 I OH = −3 mA VOL Output LOW 10% V CC 0.5 V Min I OL = 24 mA Voltage IIH Input HIGH 5.0 µAM a x V IN = 2.7V Current IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V Breakdown Test ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V IOZH Output Leakage Current 50 µAM a x V OUT = 2.7V IOZL Output Leakage Current −50 µAM a x V OUT = 0.5V IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V IZZ Bus Drainage Test 500 µA0 . 0 V V OUT = 5.25V ICCZ Power Supply Current 55 86 mA Max V O = HIGH Z

www.fairchildsemi.com 4 74F374 AC Operating Requirements Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF C L = 50 pF Min Typ Max Min Max Min Max fMAX Maximum Clock Frequency 100 140 60 70 MHz ns ns Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V V CC = +5.0V Min Max Min Max Min Max tS(H) Setup Time, HIGH or LOW 2.0 2.5 2.0 ns tS(L) D n to CP 2.0 2.0 2.0 tH (H) Hold Time, HIGH or LOW 2.0 2.0 2.0 tH (L) D n to CP 2.0 2.5 2.0 tW (H) CP Pulse Width 7.0 7.0 7.0 ns tW (L) HIGH or LOW 6.0 6.0 6.0

5 www.fairchildsemi.com 74F374 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D

www.fairchildsemi.com 6 74F374 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

7 www.fairchildsemi.com 74F374 Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com