74F323 PHILIPS | Alldatasheet
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Philips Semiconductors Product specification 74F3238-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
11990 Mar 01 853-0367 98987
FEATURES
- Common parallel I/O for reduced pin count
- Additional serial inputs and outputs for expansion
- Four operating modes: Shift left, shift right, load, and store
- 3-State outputs for bus-oriented applications
DESCRIPTION
The 74F323 is an 8-bit universal shift/storage register with 3-State outputs. Its function is similar to the 74F299 with the exception of synchronous Reset. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin counts. Separate serial inputs and outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. Four modes of operation are possible: Hold (store), shift left, shift right, and parallel load. The 74F323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load, and hold operations. The type of operation is determined by S0 and S1, as shown in the Function Table. All flip-flop outputs are brought out through 3-State buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A Low signal on SR overrides the Select and inputs and allows the flip-flops to be reset by the next rising edge of clock. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of clock are observed. A High signal on either OE0 or OE1 disables the 3-State buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-State buffers are also disabled by High signals on both S0 and S1 in preparation for a parallel load operation. PIN CONFIGURA TION 10 11
1 VCC
(TOTAL) 74F323 115MHz 55mA
ORDERING INFORMATION
DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 20-pin plastic DIP N74F323N 20-pin plastic SOL N74F323D INPUT AND OUTPUT LOADING AND F AN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW DS0 Serial data input for right shift 1.0/1.0 20µA/0.6mA DS7 Serial data input for left shift 1.0/1.0 20µA/0.6mA S0, S1 Mode select inputs 1.0/2.0 20µA/1.2mA CP Clock pulse input (Active rising edge) 1.0/1.0 20µA/0.6mA SR Synchronous Reset input (Active Low) 1.0/1.0 20µA/0.6mA OE 0, OE1 Output Enable input (Active Low) 1.0/1.0 20µA/0.6mA Q0, Q7 Serial outputs 50/33 20µA/20mA I/On Multiplexed parallel data inputs or 3.5/1.0 70µA/0.6mA I/On 3-State parallel outputs 150/40 3.0mA/24mA
Philips Semiconductors Product specification 74F3238-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
1990 Mar 01 2
I/O0 I/O2 I/O4 I/O6I/O1 I/O3 I/O5 I/O7 CP OE0 OE1 SR VCC = Pin 20 GND = Pin 10 8 17 SF00889 LOGIC SYMBOL (IEEE/IEC) SF00890 & 3EN13 C4/1→ /2← 9 4R SRG8 1, 4D 1 0 3, 4D 5, 13 3, 4D 6, 13 3, 4D 12, 13 2, 4D Z6Z6 Z12 FUNCTION TABLE INPUTS OPERATING MODE O En SR S1 S0 CP OPERATING MODE L L X X ↑ Synchronous Reset; Q0 - Q7 = Low L H H H ↑ Parallel load; I/On → Qn L H L H ↑ Shift right; DS0 →/n636861720000000000000000Q0, Q0 →/n636861720000000000000000Q1, etc. L H H L ↑ Shift left; DS7 → Q7, Q7 → Q6, etc. L H L L X Hold H X X X X Outputs disabled (3-state) H = High voltage level L = Low voltage level X = Don’t care ↑ = Low-to-High clock transition
Philips Semiconductors Product specification 74F3238-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
1990 Mar 01 3
Q I/O7 D CP Q I/O6D CP Q I/O5D CP Q I/O4D CP Q I/O3D CP Q I/O2D CP Q I/O1D CP Q I/O0D CP Q0CP DS0 OE 1 OE 0 DS7 SF00883 VCC = Pin 20 GND = Pin 10 SR 9
Philips Semiconductors Product specification 74F3238-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
1990 Mar 01 4
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to +5.5 V IOUT Current applied to output in Low output state Q0, Q7 40 mA IOUT Current applied to output in Low output state I/On 48 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature –65 to +150 °C RECOMMENDED OPERA TING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN NOM MAX VCC Supply voltage 4.5 5.0 5.5 V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current Q0, Q7 –1 mA IOH High-level output current I/On –3 mA IOL Low-level output current Q0, Q7 20 mA IOL Low-level output current I/On 24 mA Tamb Operating free-air temperature range 0 70 °C
Philips Semiconductors Product specification 74F3238-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
1990 Mar 01 5
DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS 1 LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS 1 MIN TYP 2 MAX UNIT VOH High-level output voltage Q0, Q7 VCC = MIN, VIL = MAX, VIH = MIN IOH = –1mA ±10%V CC 2.5 V VOH High-level output voltage Q0, Q7 VCC = MIN, VIL = MAX, VIH = MIN IOH = –1mA ±5%V CC 2.7 3.4 V VOH High-level output voltage I/On VIL = MAX, VIH = MIN IOH = –3mA ±10%V CC 2.5 V I/On VIH = MIN IOH = –3mA ±5%V CC 2.7 3.4 V VOL Low-level output voltage VCC = MIN, VIL = MAX, VIH = MIN IOL = MAX ±10%V CC 0.35 0.50 V VOL Low-level output voltage VIL = MAX, VIH = MIN IOL = MAX ±5%V CC 0.35 0.50 V VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V II Input current at maximum input voltage others VCC = MAX, VI = 7.0V 100 µA II Input current at maximum input voltage I/On VCC = 5.5V, VI = 5.5V 1 mA IIH High-level input currentexcept I/On VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current S0, S1 VCC = MAX, VI = 0.5V –1.2 mA IIL Low-level input current others VCC = MAX, VI = 0.5V –0.6 mA IIH + IOZH Off-state output current, High-level voltage applied I/On only VCC = MAX, VO = 2.7V 70 µA IIL + IOZL Off-state output current Low-level voltage applied only VCC = MAX, VO = 0.5V –0.6 mA IOS Short-circuit output current3 VCC = MAX –60 –150 mA ICCH VCC = MAX 55 75 mA ICC Supply current (total) ICCL VCC = MAX 65 90 mA ICCZ CC = MAX 55 85 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb =+ 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
Philips Semiconductors Product specification 74F3238-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
1990 Mar 01 6
AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Tamb = 0°C to +70°C UNITSYMBOL PARAMETER TEST CONDITIONS VCC = +5.0V VCC = +5.0V ± 10% UNIT C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX fMAX Maximum clock frequency I/O W aveform 1 70 100 70 MHz fMAX Maximum clock frequency Qn W aveform 1 85 115 85 MHz tPLH tPHL Propagation delay CP to Q0 or Q7 W aveform 1 4.0 3.5 6.0 6.0 8.5 8.5 3.5 4.5 9.5 9.5 ns ns tPLH tPHL Propagation delay CP to I/On W aveform 1 4.0 5.0 6.0 6.5 9.0 9.5 4.0 4.0 10.0 10.0 ns ns tPZH tPZL Output Enable time Sn, OE to I/On W aveform 3 W aveform 4 3.5 4.0 6.0 8.0 9.0 11.0 3.5 4.0 10.0 11.5 ns ns tPHZ tPLZ Output Disable time Sn, OE to I/On W aveform 3 W aveform 4 2.5 1.5 5.0 3.0 7.5 5.5 2.5 1.5 8.0 6.5 ns ns AC SETUP REQUIREMENTS SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Tamb = 0°C to +70°C UNITSYMBOL PARAMETER TEST CONDITIONS VCC = +5.0V VCC = +5.0V ± 10% UNIT C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX ts(H) ts(L) Setup time, High or Low S0 or S1 to CP W aveform 2 6.5 6.5 7.5 7.5 ns th(H) th(L) Hold time, High or Low S0 or S1 to CP W aveform 2 0 0 ns ts(H) ts(L) Setup time, High or Low I/O0, DS0 or DS7 to CP W aveform 2 3.5 3.5 4.0 4.0 ns th(H) th(L) Hold time, High or Low I/O0, DS0 or DS7 to CP W aveform 2 0 0 ns ts(H) ts(L) Setup time, High or Low SR to CP W aveform 2 7.0 7.0 8.5 8.5 ns th(H) th(L) Hold time, High or Low SR to CP W aveform 2 0 0 ns tw (H) tw (L) CP Pulse width, High or Low W aveform 1 3.5 3.5 4.0 4.0 ns
Philips Semiconductors Product specification 74F3238-bit universal shift/storage register with synchronous reset and common I/O pins (3-State)
1990 Mar 01 7
For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. tPLHtPHL VM VM VM VM 1/fMAX tW (L) CP Q0, Q7, I/On tW (H) SF00884 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency VM VM VM VM VMVM S0, S1, DS L, DSR , I/On, SR CP SF00885 ts(H) t h(H) th(L)ts(L) Waveform 2. Data, Select and Reset Setup and Hold Times VM VM VM tPHZtPZH Sn, OEn I/On VOH -0.3V SF00886 Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level VM VM VM tPLZtPZL Sn, OEn I/On VOL +0.3V SF00887 Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level TEST CIRCUIT AND W AVEFORM tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns Input Pulse Definition VCC family 74F D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test Circuit for 3-State Outputs DEFINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = T ermination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude 3.0V 1.5V VM R L 7.0V SF00777 TEST SWITCH tPLZ closed tPZL closed All other open SWITCH POSITION