74F323 FAIRCHILD | Alldatasheet

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■ Common parallel I/O for reduced pin count ■ Additional serial inputs and outputs for expansion ■ Four operating modes: shift left, shift right, load and store ■ 3-STATE outputs for bus-oriented applications Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F323SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F323PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2 74F323 Unit Loading/Fan Out Functional Description The 74F323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S 0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q 0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE 1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, load, hold and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S 0 and S1 in preparation for a paral- lel load operation. Mode Select Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial /c17 = LOW-to-HIGH transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA DS 0 Serial Data Input for Right Shift 1.0/1.0 20 µA/−0.6 mA DS 7 Serial Data Input for Left Shift 1.0/1.0 20 µA/−0.6 mA S0, S1 Mode Select Inputs 1.0/2.0 20 µA/−1.2 mA SR Synchronous Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA OE 1, OE2 3-STATE Output Enable Inputs (Active LOW) 1.0/1.0 20 µA/−0.6 mA I/O0–I/O7 Multiplexed Parallel Data Inputs 3.5/1.083 70 µA/−0.65 mA 3-STATE Parallel Data Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) Q 0, Q7 Serial Outputs 50/33.3 −1 mA/20 mA Inputs Response SR S1 S0 CP LXX /c17 Synchronous Reset; Q0–Q 7 = LOW HHH /c17 Parallel Load; I/On → Qn HLH /c17 Shift Right; DS0 → Q0, Q0 → Q1, etc. HHL /c17 Shift Left; DS7 → Q7, Q7 → Q6, etc. H L L X Hold

3 www.fairchildsemi.com 74F323 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.5 VM i n IOH = −1 mA (Q 0, Q7) Voltage 10% V CC 2.4 I OH = −3 mA (I/On) 5% VCC 2.7 I OH = −1 mA (Q 0, Q7) 5% VCC 2.7 I OH = −3 mA (I/On) VOL Output LOW 10% V CC 0.5 VM i n IOL = 20 mA (Q 0, Q7) Voltage 10% V CC 0.5 I OL = 24 mA (I/On) IIH Input HIGH Current 5.0 µAM a x V IN = 2.7V IBVI Input HIGH Current 7.0 µAM a x V IN = 7.0V (Non I/O Inputs) Breakdown Test IBVIT Input HIGH Current 0.5 mA Max V IN = 5.5V (I/O Inputs) Breakdown (I/O) ICEX Output HIGH 50 µAM a x V OUT = VCCLeakage Current VID Input Leakage 4.75 V 0.0 IID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V (CP, DS0, DS7, SR, OE1, OE2) −1.2 mA Max V IN = 0.5V (S0, S1) IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V IZZ Bus Drainage Test 500 µA0 . 0 V V OUT = 5.25V ICCH Power Supply Current 68 95 mA Max V O = HIGH ICCL Power Supply Current 68 95 mA Max V O = LOW ICCZ Power Supply Current 68 95 mA Max V O = HIGH Z

www.fairchildsemi.com 4 74F323 AC Operating Requirements Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max fMAX Maximum Input Frequency 70 100 70 MHz ns ns tPZH Output Enable Time 3.5 9.0 3.5 10.0 ns tPZL Sn to I/On 4.0 10.0 4.0 11.0 tPHZ Output Disable Time 2.5 6.0 2.5 7.0 ns tPLZ Sn to I/On 1.0 5.5 1.5 6.5 Symbol Parameter TA = +25°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V Min Max Min Max tS(H) Setup Time, HIGH or LOW 8.5 8.5 ns tS(L) S 0 or S1 to CP 8.5 8.5 tH (H) Hold Time, HIGH or LOW 0 0 tH (L) S 0 or S1 to CP 0 0 tS(H) Setup Time, HIGH or LOW 5.0 5.0 ns tS(L) I/O n, DS0, DS7 to CP 5.0 5.0 tH (H) Hold Time, HIGH or LOW 2.0 2.0 tH (L) I/O n, DS0, DS7 to CP 2.0 2.0 tS(H) Setup Time, HIGH or LOW 10.0 10.0 ns tS(L) SR to CP 10.0 10.0 tH (H) Hold Time, HIGH or LOW 0 0 tH (L) SR to CP 00 tW (H) CP Pulse Width 5.0 5.0 ns tW (L) HIGH or LOW 5.0 5.0

5 www.fairchildsemi.com 74F323 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B

www.fairchildsemi.com 6 74F323 Octal Universal Shift/Storage Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com