74F322PC

54F322DM NSC | Alldatasheet

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Features

Y Multiplexed parallel I/O ports Y Separate serial input and output Y Sign extend function Y TRI-STATE outputs for bus applications Commercial Military Package Package DescriptionNumber 74F322PC N20A 20-Lead (0.300 × Wide) Molded Dual-In-Line 54F322DM (Note 2) J20A 20-Lead Ceramic Dual-In-Line 74F322SJ (Note 1) M20D 20-Lead (0.300 × Wide) Molded Small Outline, EIAJ 54F322FM (Note 2) W20A 20-Lead Cerpack 54F322LM (Note 2) E20A 20-Lead Ceramic Leadless Chip Carrier, Type C Note 1: Devices also available in 13 × reel. Use suffix e SJX. Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB. Logic Symbols TL/F/9516–3 IEEE/IEC TL/F/9516–5 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

for DIP, SOIC and Flatpak TL/F/9516–1 Pin Assignment for LCC TL/F/9516–2

Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH/IOL RE Register Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA S/P Serial (HIGH) or Parallel (LOW) Mode Control Input 1.0/1.0 20 mA/b0.6 mA SE Sign Extend Input (Active LOW) 1.0/3.0 20 mA/b1.8 mA S Serial Data Select Input 1.0/2.0 20 mA/b1.2 mA D0,D 1 Serial Data Inputs 1.0/1.0 20 mA/b0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 mA/b0.6 mA MR Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA OE TRI-STATE Output Enable Input (Active LOW) 1.0/1.0 20 mA/b0.6 mA Q0 Bi-State Serial Output 50/33.3 b1 mA/ b20 mA I/O0 –I/O7 Multiplexed Parallel Data Inputs or 3.5/1.083 70 mA/b0.65 mA TRI-STATE Parallel Data Outputs 150/40 (33.3) b3 mA/24 mA (20 mA) Functional Description The ’F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A LOW signal on RE enables shift- ing or parallel loading, while a HIGH signal enables the hold mode. A HIGH signal on S/P enables shift right, while a LOW signal disables the TRI-STATE output buffers and en- ables parallel loading. In the shift right mode a HIGH signal on SE enables serial entry from either D 0 or D 1, as deter- mined by the S input. A LOW signal on SE enables shift right but Q 7 reloads its contents, thus performing the sign extend function required for the ’F384 Twos Complement Multiplier. A HIGH signal on OE disables the TRI-STATE output buff- ers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed. Mode Select Table Mode Inputs Outputs Q0 MR RE S/P SE SO E * CP I/O 7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Clear L X X X X L X L L L L L L L L L L X X X X H X ZZZZZZZZ L Parallel HL L X X X L I7 I6 I5 I4 I3 I2 I1 I0 I0Load Shift H L H H L L L D0 O7 O6 O5 O4 O3 O2 O1 O1 Right H L H H H L L D1 O7 O6 O5 O4 O3 O2 O1 O1 Sign HL HL XL L O7 O7 O6 O5 O4 O3 O2 O1 O1Extend Hold H H X X X L L NC NC NC NC NC NC NC NC NC *When the OE input is HIGH all I/O n terminals are at the high impedance state; sequential operation or clearing of the register is not affected. Note 1: I7 –I0 e The level of the steady-state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q 0) are isolated from the I/O terminal. Note 2: D0,D 1 e The level of the steady-state inputs to the serial multiplexer input. Note 3: O7 –O0 e The level of the respective Q n flip-flop prior to the last Clock LOW-to-HIGH transition. H e HIGH Voltage Level L e LOW Voltage Level Z e High Impedance Output State L e LOW-to-HIGH Transition NC e No Change

TL/F/9516–4 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Storage Temperature b65§Ct o a150§C Ambient Temperature under Bias b55§Ct o a125§C Junction Temperature under Bias b55§Ct o a175§C Plastic b55§Ct o a150§C VCC Pin Potential to Ground Pin b0.5V to a7.0V Input Voltage (Note 2) b0.5V to a7.0V Input Current (Note 2) b30 mA to a5.0 mA Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Voltage Applied to Output in HIGH State (with V CC e 0V) Standard Output b0.5V to V CC TRI-STATE Output b0.5V to a5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Recommended Operating Conditions Free Air Ambient Temperature Military b55§Ct o a125§C Commercial 0 §Ct o a70§C Supply Voltage Military a4.5V to a5.5V Commercial a4.5V to a5.5V Symbol Parameter 54F/74F Units V CC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage b1.2 V Min I IN eb 18 mA VOH Output HIGH 54F 10% V CC 2.5 I OH eb 1m A( Q 0, I/O n) Voltage 54F 10% V CC 2.4 I OH eb 3 mA (I/O n) 74F 10% V CC 2.5 V Min IOH eb 1m A( Q 0, I/O n) 74F 10% V CC 2.4 I OH eb 3 mA (I/O n) 74F 5% V CC 2.7 I OH eb 1m A( Q 0, I/O n) 74F 5% V CC 2.7 I OH eb 3 mA (I/O n) VOL Output LOW 54F 10% V CC 0.5 I OL e 20 mA (Q 0, I/O n) Voltage 74F 10% V CC 0.5 V Min I OL e 20 mA (Q 0) 74F 10% V CC 0.5 I OL e 24 mA ( I/O n) IIH Input HIGH 54F 20.0 mA Max VIN e 2.7V Current 74F 5.0 IBVI Input HIGH Current 54F 100 mA Max VIN e 7.0V (Non-I/O Inputs) Breakdown Test 74F 7.0 IBVIT Input HIGH Current 54F 1.0 mA Max VIN e 5.5V (I/O n) Breakdown Test (I/O) 74F 0.5 ICEX Output HIGH 54F 250 mA Max VOUT e VCC Leakage Current 74F 50 VID Input Leakage 74F 4.75 V 0.0 IID e 1.9 mA Test All Other Pins Grounded IOD Output Leakage 74F 3.75 mA 0.0 VIOD e 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current b0.6 mA Max V IN e 0.5V (RE , S/P ,D n, CP, MR ,O E ) b1.2 mA Max V INe 0.5V (S) b1.8 mA Max V INe 0.5V (SE ) IIH a Output Leakage Current 70 mA Max V I/O e 2.7V (I/O n)IOZH IIL a Output Leakage Current b650 mA Max VI/O e 0.5V (I/O n) IOZL IOS Output Short-Circuit Current b60 b150 mA Max V OUT e 0V IZZ Bus Drainage Test 500 mA 0.0V V OUT e 5.25V ICC Power Supply Current 60 90 mA Max

TA ea 25§C TA,V CC e Mil T A,V CC e ComSymbol Parameter V CC ea 5.0V CL e 50 pF C L e 50 pF Units CL e 50 pF Min Typ Max Min Max Min Max fmax Maximum Clock Frequency 70 90 50 70 MHz AC Operating Requirements 74F 54F 74F Symbol Parameter TA ea 25§C TA,V CC e Mil T A,V CC e Com UnitsVCC ea 5.0V Min Max Min Max Min Max th(H) Hold Time, HIGH or LOW 0 0 0 nsth(L) RE to CP 0 0 0 th(H) Hold Time, HIGH or LOW 0 1.0 0 nsth(L) S or S/P to CP 0 0 0 tw(H) CP Pulse Width, HIGH or LOW 7.0 8.0 7.0 nstw(L) tw(L) MR Pulse Width, LOW 5.5 7.5 6.5 trec Recovery Time 8.0 12.0 8.0 nsMR to CP

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: 74F 322 S C X Temperature Range Family Special Variations 74F e Commercial QB e Military grade device with 54F e Military environmental and burn-in processingDevice Type X e Devices shipped in 13 × reel Package Code Temperature RangeP e Plastic DIP C e Commercial (0 §Ct o a70§C)D e Ceramic DIP M e Military ( b55§Ct o a125§C)F e Flatpak SJ e Small Outline SOIC EIAJ L e Leadless Chip Carrier (LCC) Physical Dimensions inches (millimeters) 20-Lead Ceramic Leadless Chip Carrier (L)

Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Dual-In-Line Package (D)

Physical Dimensions inches (millimeters) (Continued) 20-Lead (0.300 × Wide) Molded Small Outline Package, EIAJ (SJ) 20-Lead (0.300 × Wide) Molded Dual-In-Line Package (P)

54F/74F322 Octal Serial/Parallel Register with Sign Extend Physical Dimensions inches (millimeters) (Continued) 20-Lead Ceramic Flatpak (F) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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