74F322 PHILIPS | Alldatasheet
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Technical content
Philips Semiconductors Product specification 74F3228-bit serial/parallel register with sign extend (3-State)
11988 Apr 22 853-0366 93020
FEATURES
- Multiplexed parallel I/O ports
- Separate serial input and output
- Sign extend function
- 3-State outputs for bus applications
- Direct Overriding Clear
DESCRIPTION
The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-State parallel outputs plus a bi-state serial output. Parallel data inputs and outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the clock. Four synchronous modes of operation are possible: hold (store), shift right with serial entry, shift right with sign extend, and parallel load. An asynchronous Master Reset (MR) input overrides clocked operation and clears the registers. The 74F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A Low signal on RE enables shifting or parallel loading, while a High signal enables the hold mode. A High signal on S/P enables shift right, while a Low signal disables the 3-State output buffers and enables parallel loading. In the shift right mode a High signal on SE enables serial entry from either D0 or D1, as determined by the S input. A Low signal on SE enables shift right, but Q7 reloads its contents, thus performing the sign extend function. A High signal on OE disables the 3-State output buffers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed. PIN CONFIGURA TION 10 11
1 VCC
S SE I/O7 I/O5 I/O3 I/O1 CP RE I/O6 I/O4 I/O2 I/O0 OE S/P MR GND SF00874 TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F322 125MHz 60mA
ORDERING INFORMATION
DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 20-pin plastic DIP N74F322N 20-pin plastic SOL N74F322D INPUT AND OUTPUT LOADING AND F AN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0, D1 Serial data inputs 1.0/1.0 20µA/0.6mA S Serial data select input 1.0/2.0 20µA/1.2mA SE Sign Extend input 1.0/3.0 20µA/1.8mA CP Clock Pulse input (Active rising edge) 1.0/1.0 20µA/0.6mA S/P Serial (High) or Parallel (Low) mode control input 1.0/1.0 20µA/0.6mA RE Register Enable input (Active Low) 1.0/1.0 20µA/0.6mA MR Asynchronous Master Reset input (Active Low) 1.0/1.0 20µA/0.6mA OE Output Enable input (Active Low) 1.0/1.0 20µA/0.6mA Q7 Bi-state serial output 50/33 1.0mA/20mA I/On Multiplexed parallel data inputs or 3.5/1.0 70µA/0.6mA I/On 3-State parallel outputs 150/40 3.0mA/24mA
Philips Semiconductors Product specification 74F3228-bit serial/parallel register with sign extend (3-State)
1988 Apr 22 2
I/O0 I/O2 I/O4 I/O6I/O1 I/O3 I/O5 I/O7 S RE S/P CP OE SE VCC = Pin 20 GND = Pin 10 SF00875 9 MR LOGIC SYMBOL (IEEE/IEC) SF00876 2EN15 C6/1 → 9 R SRG8 8, 4, 1, 6D19 2, 6D 12, 13 Z14 3M1[SHIFT] 3M2[PAR LOAD] 2, 96D 8, 15 Z8 8, 5, 1, 6D 8, 4, 1, 6D 2, 6D 7, 15 FUNCTION TABLE INPUTS INPUTS OPERATING MODEMR RE S/P SE S OE * CP I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Q7 OPERATING MODE L L H X X H X X X X L L X X L L L L L L L L L L L L L L L L L L Clear H L L X X X ↑ I0 I1 I2 I3 I4 I5 I6 I7 I7 Parallel load H H L L H H H H L H L L Shift right H L H L X L ↑ O0 O0 O1 O2 O3 O4 O5 O6 O6 Sign extend H H X X X L X NC NC NC NC NC NC NC NC NC Hold X X L X L X X X X X X H X Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z NC NC 3-State * = When the input is High, all I/O terminals are at the high impedance state, sequential operation or clearing of the register is not affected. H = High voltage level L = Low voltage level NC = No change X = Don’t care Z = High impedance “off” state ↑ = Low-to-High clock transition I0–I7 = The level of the steady state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q7) are isolated from the I/O terminal. D0–D7 = The level of the steady state inputs to the serial multiplexer input. O0–O7 = The level of the respective Qn flip-flop prior to the last clock Low-to-High transition. ↑ = Not a Low-to-High clock transition
Philips Semiconductors Product specification 74F3228-bit serial/parallel register with sign extend (3-State)
1988 Apr 22 3
R Q I/O0 D CP MR CP S/P RE OE SF00877 VCC = Pin 20 GND = Pin 10 Q R Q I/O1D CP Q R Q I/O2D CP Q R Q I/O3D CP Q R Q I/O4D CP Q R Q I/O5D CP Q R Q I/O6D CP Q R Q I/O7D CP Q S SE
Philips Semiconductors Product specification 74F3228-bit serial/parallel register with sign extend (3-State)
1988 Apr 22 4
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to +5.5 V IOUT Current applied to output in Low output state Q7 40 mA IOUT Current applied to output in Low output state I/On 48 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature –65 to +150 °C RECOMMENDED OPERA TING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN NOM MAX VCC Supply voltage 4.5 5.0 5.5 V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current Q7 –1 mA IOH High-level output current I/On –3 mA IOL Low-level output current Q7 20 mA IOL Low-level output current I/On 24 mA Tamb Operating free-air temperature range 0 70 °C
Philips Semiconductors Product specification 74F3228-bit serial/parallel register with sign extend (3-State)
1988 Apr 22 5
DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS 1 LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS 1 MIN TYP 2 MAX UNIT VOH High-level output voltage Q7 VCC = MIN, VIL = MAX, VIH = MIN IOH = –1mA ±10%V CC 2.5 V VOH High-level output voltage Q7 VCC = MIN, VIL = MAX, VIH = MIN IOH = –1mA ±5%V CC 2.7 3.4 V VOH High-level output voltage I/On VIL = MAX, VIH = MIN IOH = –3mA ±10%V CC 2.4 V I/On VIH = MIN IOH = –3mA ±5%V CC 2.7 3.3 V VOL Low-level output voltage VCC = MIN, VIL = MAX, VIH = MIN IOL = MAX ±10%V CC 0.38 0.55 V VOL Low-level output voltage VIL = MAX, VIH = MIN IOL = MAX ±5%V CC 0.35 0.50 V VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V II Input current at maximum input voltage others VCC = MAX, VI = 7.0V 100 µAInput current at maximum input voltage I/On VCC = MAX, VI = 5.5V 1 mA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current SE VCC = MAX, VI = 0.5V –1.8 mA IIL Low-level input current S VCC = MAX, VI = 0.5V –1.2 mAIL others CC = MAX, VI = 0.5V –0.6 mA IIH + IOZH Off-state output current High-level voltage applied VCC = MAX, VI = 2.7V 70 µA IIL + IOZL Off-state output current Low-level voltage applied VCC = MAX, VI = 0.5V –0.6 mA IOS Short-circuit output current3 VCC = MAX –60 –150 mA ICCH VCC = MAX 50 75 mA ICC Supply current (total) ICCL VCC = MAX 60 90 mA ICCZ CC = MAX 65 95 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
Philips Semiconductors Product specification 74F3228-bit serial/parallel register with sign extend (3-State)
1988 Apr 22 6
AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Tamb = 0°C to +70°C UNITSYMBOL PARAMETER TEST CONDITIONS VCC = +5.0V VCC = +5.0V ± 10% UNIT C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX fMAX Maximum clock frequency W aveform 1 110 125 90 MHz tPLH tPHL Propagation delay CP to I/On W aveform 1 4.0 4.5 6.0 7.0 9.0 9.5 4.0 4.5 10.0 10.0 ns ns tPLH tPHL Propagation delay CP to Q7 W aveform 1 4.5 5.0 6.5 6.5 9.0 9.0 4.5 5.0 10.0 9.0 ns ns tPHL Propagation delay tPHL Propagation delay tPZH tPZL Output Enable time OE to I/On W aveform 4 W aveform 5 3.0 5.5 5.0 7.5 8.0 10.5 3.0 5.0 9.0 11.0 ns ns tPHZ tPLZ Output Disable time OE to I/On W aveform 4 W aveform 5 2.0 1.0 4.0 2.5 6.5 5.5 2.0 1.0 7.5 6.0 ns ns tPZH tPZL Output Disable time S/P to I/On W aveform 4 W aveform 5 4.0 6.0 6.0 8.0 9.0 11.0 3.5 5.5 10.0 11.5 ns ns tPHZ tPLZ Output Disable time S/P to I/On W aveform 4 W aveform 5 4.0 2.0 6.0 4.0 9.0 7.0 3.5 2.0 10.5 7.5 ns ns tPZH tPZL Output Disable time RE to I/On W aveform 4 W aveform 5 8.0 9.0 9.5 11.0 12.5 14.0 7.0 8.0 14.0 16.0 ns ns tPHZ tPLZ Output Disable time RE to I/On W aveform 4 W aveform 5 6.5 4.5 8.5 6.5 11.5 9.5 5.5 4.0 13.0 10.5 ns ns
Philips Semiconductors Product specification 74F3228-bit serial/parallel register with sign extend (3-State)
1988 Apr 22 7
SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS Tamb = +25°C Tamb = 0°C to +70°C UNITSYMBOL PARAMETER TEST CONDITIONS VCC = +5.0V VCC = +5.0V ± 10% UNIT C L = 50pF, RL = 500Ω C L = 50pF, RL = 500Ω MIN TYP MAX MIN MAX ts(H) ts(L) Setup time, High or Low RE to CP W aveform 3 8.0 12.5 9.5 14.0 ns ns th(H) th(L) Hold time, High or Low RE to CP W aveform 3 0 ns ns ts(H) ts(L) Setup time, High or Low D0, D1 or I/On to CP W aveform 3 4.0 4.5 6.0 5.0 ns ns th(H) th(L) Hold time, High or Low D0, D1 or I/On to CP W aveform 3 0 ns ns ts(H) ts(L) Setup time, High or Low SE to CP W aveform 3 5.5 5.0 7.0 5.5 ns ns th(H) th(L) Hold time, High or Low SE to CP W aveform 3 0 ns ns ts(H) ts(L) Setup time, High or Low S/P to CP W aveform 3 10.5 9.5 11.0 10.5 ns ns ts(H) ts(L) Setup time, High or Low S to CP W aveform 3 4.0 8.5 4.5 9.5 ns ns th(H) th(L) Hold time, High or Low S or S/P to CP W aveform 3 0 ns ns tw (H) tw (L) CP Pulse width, High or Low W aveform 3 5.0 5.0 5.0 5.0 ns tw (L) MR Pulse width, Low W aveform 3 5.0 5.0 ns tREC Recovery time, MR to CP W aveform 2 4.0 4.5 ns
Philips Semiconductors Product specification 74F3228-bit serial/parallel register with sign extend (3-State)
1988 Apr 22 8
For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance. VM tPLHtPHL VM VM VM 1/fMAX tW (L) CP Q7, I/On tW (H) SF00878 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency VM VM VM tPHL tW (L) tREC VM Q7, I/On CP MR SF00879 Waveform 2. Master Reset Pulse Width, Master Reset to Output Delay, and Master Reset to Clock Recovery Time VM VM VM VM ts(H) t h(H) th(L)ts(L) VMVM RE , D0, D1, I/On, SE , S/P, S CP SF00880 Waveform 3. Data Setup and Hold Times VM VM VM tPHZtPZH RE , S/P, OE I/On VOH -0.3V SF00881 Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level VM VM VM tPLZtPZL I/On VOL +0.3V SF00882 RE , S/P, OE Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
Philips Semiconductors Product specification 74F3228-bit serial/parallel register with sign extend (3-State)
1988 Apr 22 9
TEST CIRCUIT AND W AVEFORM tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns Input Pulse Definition VCC family 74F D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test Circuit for 3-State Outputs DEFINITIONS: R L = Load resistor; see AC electrical characteristics for value. C L = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. R T = T ermination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude 3.0V 1.5V VM R L 7.0V SF00777 TEST SWITCH tPLZ closed tPZL closed All other open SWITCH POSITION