74F322 FAIRCHILD | Alldatasheet
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■ Multiplexed parallel I/O ports ■ Separate serial input and output ■ Sign extend function ■ 3-STATE outputs for bus applications Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F322PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com 2 74F322 Unit Loading/Fan Out Functional Description The 74F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A LOW signal on RE enables shift- ing or parallel loading, while a HIGH signal enables the hold mode. A HIGH signal on S/P enables shift right, while a LOW signal disables the 3-STATE output buffers and enables parallel loading. In the shift right mode a HIGH sig- nal on SE enables serial entry from either D0 or D1, as determined by the S input. A LOW signal on SE enables shift right but Q7 reloads its contents, thus performing the sign extend function required for the 74F384 Twos Com- plement Multiplier. A HIGH signal on OE disables the 3- STATE output buffers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed. Mode Select Table H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance Output State /c17 = LOW-to-HIGH Transition NC = No Change Note: I7–I0 = The level of the steady-state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs (except Q0) are isolated from the I/O terminal. Note: D0, D1 = The level of the steady-state inputs to the serial multiplexer input. Note: O7–O 0 = The level of the respective Qn flip-flop prior to the last Clock LOW-to-HIGH transition. Note 1: When the OE input is HIGH all I/On terminals are at the high impedance state; sequential operation or clearing of the register is not affected. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH /IOL RE Register Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA S/P Serial (HIGH) or Parallel (LOW) Mode Control Input 1.0/1.0 20 µA/−0.6 mA SE Sign Extend Input (Active LOW) 1.0/3.0 20 µA/−1.8 mA S Serial Data Select Input 1.0/2.0 20 µA/−1.2 mA D 0, D1 Serial Data Inputs 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA MR Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA OE 3-STATE Output Enable Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA Q 0 Bi-State Serial Output 50/33.3 −1 mA/−20 mA I/O0–I/O7 Multiplexed Parallel Data Inputs or 3.5/1.083 70 µA/−0.65 mA 3-STATE Parallel Data Outputs 150/40 (33.3) −3 mA/24 mA (20 mA) Mode Inputs Outputs Q 0MR RE S/P SE SO E (Note 1) CP I/O 7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 C l e a r LXXXX L XLLLLLLLLL LXXXX H XZZZZZZZZL Parallel H L L X X X /c17 I7 I6 I5 I4 I3 I2 I1 I0 I0 Load Shift H L H H L L /c17 D 0 O 7 O 6 O 5 O 4 O 3 O 2 O 1 O 1 Right H L H H H L /c17 D 1 O 7 O 6 O 5 O 4 O 3 O 2 O 1 O 1 Sign H L H L X L /c17 O 7 O 7 O 6 O 5 O 4 O 3 O 2 O 1 O 1 Extend Hold H H X X X L /c17 NC NC NC NC NC NC NC NC NC
3 www.fairchildsemi.com 74F322 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com 4 74F322 Absolute Maximum Ratings(Note 2) Recommended Operating Conditions Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 3) −0.5V to +7.0V Input Current (Note 3) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH Voltage 10% V CC 2.5 VM i n IOH = −1 mA (Q0, I/On) 10% V CC 2.4 I OH = −3 mA (I/On) 5% V CC 2.7 I OH = −1 mA (Q0, I/On) 5% V CC 2.7 I OH = −3 mA (I/On) VOL Output LOW Voltage 10% V CC 0.5 V Min I OL = 20 mA (Q0) 10% V CC 0.5 I OL = 24 mA (I/On) IIH Input HIGH Current 5.0 µAM a x V IN = 2.7V IBVI Input HIGH Current Breakdown Test 7.0 µAM a x V IN = 7.0V (Non-I/O Inputs) IBVIT Input HIGH Current Breakdown Test (I/O) 0.5 mA Max V IN = 5.5V (I/On) ICEX Output HIGH Leakage Current 50 µAM a x V OUT = VCC VID Input Leakage 4.75 V 0.0 I ID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 V IOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max VIN = 0.5V (RE, S/P, Dn, CP, MR, OE) −1.2 mA Max V IN= 0.5V (S) −1.8 mA Max VIN= 0.5V (SE) IIH + Output Leakage Current 70 µAM a x V I/O = 2.7V (I/On) IOZH IIL + Output Leakage Current −650 µAM a x V I/O = 0.5V (I/On) IOZL IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V IZZ Bus Drainage Test 500 µA0 . 0 V V OUT = 5.25V ICC Power Supply Current 60 90 mA Max
5 www.fairchildsemi.com 74F322 AC Operating Requirements Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0°C to +75°C Units VCC = +5.0V C L = 50 pF C L = 50 pF C L = 50 pF Min Typ Max Min Max Min Max fMAX Maximum Clock Frequency 70 90 50 70 MHz MR to I/On MR to Q0 Symbol Parameter TA = +25°CT A = −55°C to +125°CT A = 0C to +75°C UnitsVCC = +5.0V Min Max Min Max Min Max tS(H) Setup Time, HIGH or LOW 6.0 14.0 7.0 nstS(L) RE to CP 14.0 18.0 16.0 tH (H) Hold Time, HIGH or LOW 0 0 0 nstH (L) RE to CP 000 tS(H) Setup Time, HIGH or LOW 6.5 8.5 7.5 ns tS(L) D 0, D1 or I/On to CP 6.5 8.5 7.5 tH (H) Hold Time, HIGH or LOW 2.0 3.0 3.0 ns tH (L) D 0, D1 or I/On to CP 2.0 3.0 3.0 tSH) Setup Time, HIGH or LOW 7.0 9.0 8.0 nstS(L) SE to CP 2.5 11.0 3.5 tH (H) Hold Time, HIGH or LOW 2.0 2.0 2.0 nstH (L) SE to CP 0.0 1.0 0.0 tS(H) Setup Time, HIGH or LOW 11.0 13.0 12.0 nstS(L) S/P to CP 13.5 21.0 15.5 tS(H) Setup Time, HIGH or LOW 6.5 8.5 7.5 ns tS(L) S to CP 9.0 11.0 10.0 tH (H) Hold Time, HIGH or LOW 0 1.0 0 nstH (L) S or S/P to CP 000 tW (H) CP Pulse Width, HIGH or LOW 7.0 8.0 7.0 ns tW (L) tW (L) MR Pulse Width, LOW 5.5 7.5 6.5 tREC Recovery Time 8.0 12.0 8.0 ns MR to CP
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 74F322 Octal Serial/Parallel Register with Sign Extend LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A