74F132 FAIRCHILD | Alldatasheet

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© 1999 Fairchild Semiconductor Corporation DS009477 www.fairchildsemi.com April 1988 Revised July 1999 74F132 Quad 2-Input NAND Schmitt Trigger 74F132 Quad 2-Input NAND Schmitt Trigger General Description The F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL out- put levels. They are capable of transforming slowly chang- ing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin than conventional NAND gates. Each circuit contains a 2-input Schmitt Trigger followed by level shifting circuitry and a standard FAST output struc- ture. The Schmitt Trigger uses positive feedback to effec- tively speed-up slow input transitions, and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and negative-going input threshold (typically 800 mV) is deter- mined by resistor ratios and is essentially insensitive to temperature and supply voltage variations. Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol IEEE/IEC Unit Loading/Fan Out Connection Diagram Function Table H = HIGH Voltage Level L = LOW Voltage Level FAST  is a registered trademark of Fairchild Semiconductor Corporation Order Number Package Number Package Description 74F132SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F132SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F132PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH /IOL An, Bn Inputs 1.0/1.0 20 µA/−0.6 mA O n Outputs 50/33.3 −1 mA/20 mA Inputs Outputs AB O LL H LH H HL H HH L

www.fairchildsemi.com 2 74F132 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) ESD Last Passing Voltage (Min) 4000V Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VT+ Positive-going Threshold 1.5 2.0 V 5.0 VT− Negative-going Threshold 0.7 1.1 V 5.0 ΔVT Hysteresis (VT + − VT −)0 . 4 V 5 . 0 VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 10% V CC 2.5 V Min I OH = −1 mA Voltage 5% V CC 2.7 I OH = −1 mA VOL Output LOW Voltage 10% V CC 0.5 V Min I OL = 20 mA IIH Input HIGH Current 5.0 µAM a x V IN = 2.7V IBVI Input HIGH Current Breakdown Test 7.0 µAM a x V IN = 7.0V ICEX Output HIGH Leakage Current 50 µAM a x V OUT = VCC VID Input Leakage Test 4.75 V 0.0 IID = 1.9 µA All Other Pins Grounded IOD Output Leakage Circuit Current 3.75 µA0 . 0 VIOD = 150 mV All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V ICCH Power Supply Current 17.0 mA Max V O = HIGH ICCL Power Supply Current 18.0 mA Max V O = LOW Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max tPLH Propagation Delay 4.0 10.5 3.5 12.0 nstPHL An, Bn to On 5.0 12.5 5.0 13.0

3 www.fairchildsemi.com 74F132 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

www.fairchildsemi.com 4 74F132 Quad 2-Input NAND Schmitt Trigger Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com