SN74F125_07 TI | Alldatasheet

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SDFS016B – JANUARY 1989 – REVISED JULY 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE ) input is high.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – N Tube SN74F125N SN74F125N SOIC D Tube SN74F125D F125 0°C to 70°C SOIC – D Tape and reel SN74F125DR F125 SOP – NS Tape and reel SN74F125NSR 74F125 SSOP – DB Tape and reel SN74F125DBR F125 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each buffer) INPUTS OUTPUT OE A Y L H H L LL H X Z Copyright  2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. D, DB, N, OR NS PACKAGE (TOP VIEW) 1OE 2OE GND V CC 4OE 3OE

SDFS016B – JANUARY 1989 – REVISED JULY 2002

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logic diagram (positive logic) 562A 2Y 2OE 231A 1Y 1OE 983A 3Y 3OE 12 114A 4Y 4OE absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current – 15 mA IOL Low-level output current 64 mA TA Operating free-air temperature 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

SDFS016B – JANUARY 1989 – REVISED JULY 2002 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK VCC = 4.5 V, II = –18 mA –1.2 V VCC =45V IOH = – 3 mA 2.4 3.3 VOH VCC = 4.5 V IOH = – 15 mA 2 3.1 V VCC = 4.75 V, IOH = – 3 mA 2.7 VOL VCC = 4.5 V, IOL = 64 mA 0.4 0.55 V II VCC = 0, VI = 7 V 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 µA IIL VCC = 5.5 V, VI = 0.5 V –20 µA IOZH VCC = 5.5 V, VO = 2.7 V 50 µA IOZL VCC = 5.5 V, VO = 0.5 V –50 µA IOS ‡ VCC = 5.5 V, VO = 0 –100 –225 mA ICCH VCC = 5.5 V, Outputs open 17 24 mA ICCL VCC = 5.5 V, Outputs open 28 40 mA ICCZ VCC = 5.5 V, Outputs open 25 35 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, C L = 50 pF, R L = 500 Ω , TA = 25°C VCC = 4.5 V to 5.5 V, C L = 50 pF, R L = 500 Ω , TA = MIN to MAX§ UNIT MIN TYP MAX MIN MAX tPLH A Y 1.2 3.6 6 1.2 6.5 ns tPHL A Y 2.2 5.1 7.5 2.2 8 ns tPZH OE Y ns tPZL OE Y 3.2 5.6 8 3.2 9 ns tPHZ OE Y 1 3.1 5 1 6 ns tPLZ OE Y 1 3.1 5.5 1 6 ns § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

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NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms

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Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN74F125D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F125DE4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F125DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F125DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F125DRE4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F125DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F125N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74F125NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74F125NSR ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74F125NSRE4 ACTIVE SO NS 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 23-Apr-2007 Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 1

Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN74F125DR D 14 MLA 330 16 6.5 9.0 2.1 8 16 Q1 SN74F125NSR NS 14 MLA 330 16 8.2 10.5 2.5 12 16 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74F125DR D 14 MLA 342.9 336.6 28.58 SN74F125NSR NS 14 MLA 342.9 336.6 28.58 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 2