74F114 PHILIPS | Alldatasheet
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Philips Semiconductors Product specification 74F114Dual J-K negative edge-triggered flip-flop with common clock and reset
11996 Mar 14 853–0340 16572
DESCRIPTION
The 74F114, Dual Negative edge-triggered JK-Type Flip-Flop with common clock and reset inputs, features individual J, K, Clock (CP), Set (SD) and Reset (RD) inputs, true and complementary outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table regardless of the level at the other inputs. A High level on the clock (CP) input enables the J and K inputs and data will be accepted. The logic levels and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CP TYPE TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74F114 100MHz 15mA PIN CONFIGURATION GND VCC SD1 Q 1 CP R D Q 0 SD0 SF00110
ORDERING INFORMATION
VCC = 5V ±10%, Tamb = 0°C to +70°C PKG. DWG. # 14-pin plastic DIP N74F114N SOT27-1 14-pin plastic SO N74F114D SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW J0, J1 J inputs 1.0/1.0 20µA/0.6mA K0, K1 K inputs 1.0/1.0 20µA/0.6mA SD0, SD1 Set inputs (active Low) 1.0/5.0 20µA/3.0mA R D Reset input (active Low) 1.0/10.0 20µA/6.0mA CP Clock Pulse input (active falling edge) 1.0/8.0 20µA/4.8mA Q0, Q0; Q1, Q1 Data outputs 50/33 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC SYMBOL Q0 Q0 Q1 Q1 56 98 VCC = Pin 14 GND = Pin 7 CP SD0 RD0 SD1 J1 K0 21 2 SF00111 K1J0 31 1 IEC/IEEE SYMBOL SF00112 S 1 R 13 C1
Philips Semiconductors Product specification 74F114Dual J-K negative edge-triggered flip-flop with common clock and reset
1996 Mar 14 2
Q SD K Q R D J CP SF00113 TO OTHER FLIP-FLOP FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE SD R D CP J K Q Q OPERATING MODE L H X X X H L Asynchronous Set H L X X X L H Asynchronous Reset L L X X X H* H* Undetermined * H H ↓ h l q q Toggle H H ↓ l h L H Load “0” (Reset) H H ↓ h l H L Load “1” (Set) H H ↓ l l q q Hold “no change” H = High voltage level h = High voltage level one setup time prior to High-to-Low clock transition L = Low voltage level l = Low voltage level one setup time prior to High-to-Low clock transition q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition X = Don’t care ↓ = High-to-Low clock transition Asynchronous inputs: Low input to S D sets Q to High level, Low input to RD sets Q to Low level Set and Reset are independent of clock Simultaneous Low on both SD and RD makes both Q and Q High. * = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously. ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 40 mA Tamb Operating free-air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C
Philips Semiconductors Product specification 74F114Dual J-K negative edge-triggered flip-flop with common clock and reset
1996 Mar 14 3
RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNITSYMBOL PARAMETER MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA Tamb Operating free-air temperature range 0 +70 °C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS 1 LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS 1 MIN TYP 2 MAX UNIT VOH High-level output voltage VCC = MIN, VIL = MAX ±10%V CC 2.5 VVOH High-level output voltage VIH = MIN, IOH = MAX ±5%V CC 2.7 3.4 V VOL Low-level output voltage VCC = MIN, VIL = MAX ±10%V CC 0.35 0.50 VVOL Low-level output voltage VIH = MIN, IOL = MAX ±5%V CC 0.35 0.50 V VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V II Input current at maximum input voltageVCC = MAX, VI = 7.0V 100 µA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA I Lll i Jn, Kn V MAX V 0 5V –0.6 mA IIL Low-level input current CP VCC = MAX V I=05 V –4.8 mA IIL Low-level input current SDn VCC = MAX , VI = 0.5V –3.0 mA R D –6.0 mA IOS Short-circuit output current3 VCC = MAX –60 –150 mA ICC Supply current (total)4 VCC = MAX 15 21 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at V CC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, I OS tests should be performed last. 4. Measure ICC with the clock input grounded and all outputs open, with the Q and Q outputs High in turn.
Philips Semiconductors Product specification 74F114Dual J-K negative edge-triggered flip-flop with common clock and reset
1996 Mar 14 4
AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TEST LIMITS UNITSYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25°C C L = 50pF, RL = 500Ω VCC = +5.0V ± 10% Tamb = 0°C to +70°C C L = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX fMAX Maximum clock frequency Waveform 1 85 100 80 MHz tPLH tPHL Propagation delay CP to Qn or Qn Waveform 1 2.0 2.0 5.0 5.5 6.5 7.5 2.0 2.0 7.5 8.5 ns tPLH tPHL Propagation delay S Dn, RD to Qn or Qn Waveform 2,3 2.0 2.0 4.5 4.5 6.5 6.5 2.0 2.0 7.5 7.5 ns AC SETUP REQUIREMENTS SYMBOL PARAMETER TEST LIMITS UNITSYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25°C C L = 50pF, RL = 500Ω VCC = +5.0V ± 10% Tamb = 0°C to +70°C C L = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX tS(H) tS(L) Setup time, High or Low Jn, K n to CP Waveform 1 4.0 3.5 5.0 4.0 ns th(H) th(L) Hold time, High or Low Jn, K n to CP Waveform 1 0.0 0.0 0.0 0.0 ns tW (H) tW (L) CP Pulse width High or Low Waveform 1 4.5 4.5 5.0 5.0 ns tW (L) SDn, RD Pulse width Low Waveform 2,3 4.5 5.0 ns tREC Recovery time S Dn, RD to CP Waveform 2,3 4.5 5.0 ns AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. VMVM CP VM VM VM VM VM VM ts(H) th(H) Jn, Kn Qn VM tw (L) fmax ts(L) t h(L) VMVM tPHL Q n tw (H) tPLH tPLHtPHL SF00114 Kn Kn Jn Jn Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Pulse Width
Philips Semiconductors Product specification 74F114Dual J-K negative edge-triggered flip-flop with common clock and reset
1996 Mar 14 5
tw (L) SF00115 Jn, Kn tREC Waveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock VM CP Qn VM VMQ n tPLH tPHL R D VMVM tw (L) SF00116 Jn, Kn tREC Waveform 3. Propagation Delay for Reset to Output, Reset Pulse Width, and Recovery Time for Reset to Clock
Philips Semiconductors Product specification 74F114Dual J-K negative edge-triggered flip-flop with common clock and reset
1996 Mar 14 6
TEST CIRCUIT AND WAVEFORMS tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns Input Pulse Definition VCC family 74F D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test Circuit for Totem-Pole Outputs DEFINITIONS: R L = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. R T = Termination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude 3.0V 1.5V VM SF00006