74F112

74F112 PHILIPS | Alldatasheet

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/C0109 /C0110 /C0114 74F112 Dual J-K negative edge-triggered flip-flop Product specification IC15 Data Handbook

1990 Feb 09

Philips Semiconductors Product specification 74F112Dual J-K negative edge-triggered flip-flop 2February 9, 1990 853–0338 98775 FEATURE

• Industrial temperature range available (–40°C to +85°C)

DESCRIPTION

The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP n is High and flip-flop will perform according to the Function Table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn. PIN CONFIGURATION 107 Q 1 VCC SD1 CP 1 R D0 R D1 CP 0 Q 0 SD0 98GND Q1 SF00103 TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74F112 100MHz 15mA

ORDERING INFORMATION

DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C PKG DWG # 16-pin plastic DIP N74F112N I74F112N SOT38-4 16-pin plastic SO N74F112D I74F112D SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW J0, J1 J inputs 1.0/1.0 20µA/0.6mA K0, K1 K inputs 1.0/1.0 20µA/0.6mA SD0, SD1 Set inputs (active Low) 1.0/5.0 20µA/3.0mA R D0, RD1 Reset inputs (active Low) 1.0/5.0 20µA/3.0mA CP 0, CP1 Clock Pulse input (active falling edge) 1.0/4.0 20µA/2.4mA Q0, Q0; Q1, Q1 Data outputs 50/33 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

Philips Semiconductors Product specification 74F112Dual J-K negative edge-triggered flip-flop February 9, 1990 3 LOGIC SYMBOL Q0 Q0 Q1 Q1 56 97VCC = Pin 16 GND = Pin 8 CP0 SD0 RD0 CP1 SD1 RD1 J1 K0 21 2 SF00104 K1J0 31 1 IEC/IEEE SYMBOL SF00105 R S R S LOGIC DIAGRAM 5, 9 4, 10 2, 12 1, 13 6, 7 15, 14 3, 11 Qn SDn Kn Q n R Dn Jn CP n SF00106 VCC = Pin 16 GND = Pin 8 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE SD R D CP J K Q Q OPERATING MODE L H X X X H L Asynchronous Set H L X X X L H Asynchronous Reset L L X X X H* H* Undetermined * H H ↓ h h q q Toggle H H ↓ l h L H Load “0” (Reset) H H ↓ h l H L Load “1” (Set) H H ↓ l l q q Hold “no change” H H H X X Q Q Hold “no change” H = High voltage level h = High voltage level one setup time prior to High-to-Low clock transition L = Low voltage level l = Low voltage level one setup time prior to High-to-Low clock transition q = Lower case letters indicate the state of the reference output prior to the High-to-Low clock transition X = Don’t care ↓ = High-to-Low clock transition * = Both outputs will be High while both S D and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously.

Philips Semiconductors Product specification 74F112Dual J-K negative edge-triggered flip-flop February 9, 1990 4 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 40 mA T O perating free air temperature range Commercial range 0 to +70 °C Tamb Operating free-air temperature range Industrial range –40 to +85 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNITSYMBOL PARAMETER MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA T O perating free air temperature range Commercial range 0 +70 °C Tamb Operating free-air temperature range Industrial range –40 +85 °C DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS 1 LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS 1 MIN TYP 2 MAX UNIT VO High level output voltage VCC = MIN, VIL = MAX ±10%V CC 2.5 VVOH High-level output voltage VIH = MIN, IOH = MAX ±5%V CC 2.7 3.4 V VO Low level output voltage VCC = MIN, VIL = MAX ±10%V CC 0.35 0.50 VVOL Low-level output voltage VIH = MIN, IOL = MAX ±5%V CC 0.35 0.50 V VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V II Input current at maximum input voltageVCC = MAX, VI = 7.0V 100 µA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA Jn, Kn –0.6 mA IIL Low-level input current CP n VCC = MAX, VI = 0.5V –2.4 mA SDn, RDn –3.0 mA IOS Short-circuit output current3 VCC = MAX –60 –150 mA ICC Supply current (total)4 VCC = MAX 15 21 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Measure ICC with the clock input grounded and all outputs open, with the Q and Q outputs High in turn.

Philips Semiconductors Product specification 74F112Dual J-K negative edge-triggered flip-flop February 9, 1990 5 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25°C C L = 50pF R L = 500Ω VCC = +5.0V ± 10% Tamb = 0°C to +70°C C L = 50pF R L = 500Ω VCC = +5.0V ± 10% Tamb = –40°C to +85°C C L = 50pF R L = 500Ω UNIT MIN TYP MAX MIN MAX MIN MAX fMAX Maximum clock frequency Waveform 1 85 100 80 80 MHz tPLH tPHL Propagation delay CP to Qn or Qn Waveform 1 2.0 2.0 5.0 5.0 6.5 6.5 2.0 2.0 7.5 7.5 2.0 2.0 7.5 7.5 ns tPLH tPHL Propagation delay S Dn, RD to Qn or Qn Waveform 2,3 2.0 2.0 4.5 4.5 6.5 6.5 2.0 2.0 7.5 7.5 1.5 1.5 7.5 7.5 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25°C C L = 50pF R L = 500Ω VCC = +5.0V ± 10% Tamb = 0°C to +70°C C L = 50pF R L = 500Ω VCC = +5.0V ± 10% Tamb = –40°C to +85°C C L = 50pF R L = 500Ω UNIT MIN TYP MAX MIN MAX MIN MAX tS(H) tS((L) Setup time, High or Low Jn, Kn to CP Waveform 1 4.0 3.5 5.0 4.0 5.0 4.0 ns th(H) th(L) Hold time, High or Low Jn, Kn to CP Waveform 1 0.0 0.0 0.0 0.0 0.0 0.0 ns tW (H) tW (L) CP Pulse width High or Low Waveform 1 4.5 4.5 5.0 5.0 5.0 5.0 ns tW (L) SDn, RD Pulse width Low Waveform 2,3 4.5 5.0 5.0 ns tREC Recovery time S Dn, RD to CP Waveform 2,3 4.5 5.0 5.0 ns AC WAVEFORMS For all waveforms, VM = 1.5V. VMVM CP n VM VM VM VM VM VM ts(H) th(H) Jn, Kn Qn VM tw (L) fmax ts(L) t h(L) VMVM tPLH Q n tw (H) tPHL tPHLtPLH SF00107 The shaded areas indicate when the input is permitted to change for predictable output performance. Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Pulse Width

Philips Semiconductors Product specification 74F112Dual J-K negative edge-triggered flip-flop February 9, 1990 6 VM CP n Qn VM VMQ n tPHL tPLH SDn VMVM tw (L) SF00108 Jn, Kn tREC Waveform 2. Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock VM CP n Qn VM VMQ n tPLH tPHL R Dn VMVM tw (L) SF00109 Jn, Kn tREC Waveform 3. Propagation Delay for Reset to Output, Reset Pulse Width, and Recovery Time for Reset to Clock

Philips Semiconductors Product specification 74F112Dual J-K negative edge-triggered flip-flop February 9, 1990 7 TEST CIRCUIT AND WAVEFORMS tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns Input Pulse Definition VCC family 74F D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test Circuit for Totem-Pole Outputs DEFINITIONS: R L = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. R T = Termination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude 3.0V 1.5V VM SF00006

Philips Semiconductors Product specification 74F112Dual J-K negative edge-triggered flip-flop

1990 Feb 09 8

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Philips Semiconductors Product specification 74F112Dual J-K negative edge-triggered flip-flop

1990 Feb 09 9

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Philips Semiconductors Product specification 74F112Dual J-K negative edge-triggered flip-flop yyyy mmm dd 10 Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Date of release: 10-98 Document order number: 9397-750-05071 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.