54F109 TI1 | Alldatasheet

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54F109,74F109 Dual JK (Note: Overbar Over the K) Positive Edge-Triggered Flip-Flop Literature Number: SNOS149A

Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed, completely indepen- dent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH

Features

n Guaranteed 4000V minimum ESD protection. Ordering Code: See Section 0 Commercial Military Package Package Description Number 74F109PC N16E 16-Lead (0.300" Wide) Molded Dual-in-Line 54F109DM (Note 2) J16A 16-Lead Ceramic Dual-in-Line 74F109SC (Note 1) M16A 16-Lead (0.150" Wide) Molded Small Outline, JEDEC 74F109SJ (Note 1) M16D 16-Lead (0.300" Wide) Molded Small Outline, EIAJ 54F109FM (Note 2) W16A 16-Lead Cerpack 54F109LM (Note 2) E20A 16-Lead Ceramic Leadless Chip Carrier, Type C Note 1:Devices also available in 13" reel. Use suffix= SCX and SJX. Note 2:Military grade device with environmental and burn-in processing. Use suffix= DMQB, FMQB and LMQB. Logic Symbols FAST ® and TRI-STATE® are registered trademarks of National Semiconductor Corporation. DS009471-3 DS009471-4 IEEE/IEC DS009471-6 November 1994 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop 54F/74F109 © 1997 National Semiconductor Corporation DS009471 www.national.com 1 PrintDate=1997/08/28 PrintTime=11:45:22 10182 ds009471 Rev. No. 1 cmservProof 1 DSXXX Obsolete

See Section 0 for U.L. definitions 54F/74F Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH /IOL J1,J2,K 1,K 2 Data Inputs 1.0/1.0 20 µA/−0.6 mA CP 1,C P2 Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA C D1 ,C D2 Direct Clear Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA SD1 ,S D2 Direct Set Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA Q 1,Q 2,Q 1,Q 2 Outputs 50/33.3 −1 mA/20 mA Truth Table Inputs Outputs SD C D CP J K QQ LHX X X HL HLX X X LH LLX X X H H HH N llL H HH N h l Toggle HH N lh Q 0 Q 0 HH N hh H L HHL X X Q 0 Q 0 H (h)= HIGH Voltage Level L (l)= LOW Voltage Level N = LOW-to-HIGH Transition X = Immaterial Q 0 (Q0) = Before LOW-to-HIGH Transition of Clock Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition. Pin Assignment for DIP, SOIC and Flatpak DS009471-1 Pin Assignment for LCC DS009471-2 PrintDate=1997/08/28 PrintTime=11:45:23 10182 ds009471 Rev. No. 1 cmservProof 2 DSXXX www.national.com 2 Obsolete

Logic Diagram(One Half Shown) DS009471-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.national.com PrintDate=1997/08/28 PrintTime=11:45:24 10182 ds009471 Rev. No. 1 cmservProof 3 Obsolete

Absolute Maximum Ratings (Note 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature −65˚C to +150˚C Ambient Temperature under Bias −55˚C to +125˚C Junction Temperature under Bias −55˚C to +175˚C Plastic −55˚C to +150˚C V CC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 4) −0.5V to +7.0V Input Current (Note 4) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC TRI-STATE® Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V Recommended Operating Conditions Free Air Ambient Temperature Military −55˚C to +125˚C Commercial 0˚C to +70˚C Supply Voltage Military +4.5V to +5.5V Commercial +4.5V to +5.5V Note 3:Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 4:Either voltage limit or current limit is sufficient to protect inputs. Symbol Parameter 54F/74F Units V CC Conditions Min Typ Max VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH 54F 10% VCC 2.5 IOH = −1 mA Voltage 74F 10 % VCC 2.5 V Min I OH = −1 mA 74F 5% VCC 2.7 IOH = −1 mA VOL Output LOW 54F 10% VCC 0.5 V Min I OL = 20 mA Voltage 74F 10% VCC 0.5 IOL = 20 mA IIH Input HIGH 54F 20.0 µA Max V IN = 2.7V Current 74F 5.0 IBVI Input HIGH Current 54F 100 µA Max V IN = 7.0V Breakdown Test 74F 7.0 ICEX Output HIGH 54F 250 µA Max V OUT = VCC Leakage Current 74F 50 VID Input Leakage 74F 4.75 V 0.0 I ID = 1.9 µA Test All Other Pins Grounded IOD Output Leakage 74F 3.75 µA 0.0 V IOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V (Jn,K n) −1.8 mA Max V IN = 0.5V (CDn ,S Dn ) IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V ICC Power Supply Current 11.7 17.0 mA Max CP = 0V See Section 0 for Waveforms and Load Configurations 74F 54F 74F TA = +25˚C T A ,V CC = Mil T A ,V CC = Com Fig. Symbol Parameter VCC = +5.0V C L = 50 pF C L = 50 pF Units No. C L = 50 pF Min Typ Max Min Max Min Max fmax Maximum Clock Frequency 100 125 70 90 MHz kk-kk PrintDate=1997/08/28 PrintTime=11:45:27 10182 ds009471 Rev. No. 1 cmservProof 4 DSXXX DSXXX www.national.com 4 Obsolete

See Section 0 for Waveforms and Load Configurations 74F 54F 74F TA = +25˚C T A ,V CC = Mil T A ,V CC = Com Fig. Symbol Parameter VCC = +5.0V C L = 50 pF C L = 50 pF Units No. C L = 50 pF Min Typ Max Min Max Min Max Q n or Qn AC Operating Requirements See Section 0 for Waveforms 74F 54F 74F Symbol Parameter TA = +25˚C T A ,V CC = Mil T A ,V CC = Com Units Fig. VCC = +5.0V No. Min Max Min Max Min Max ts(H) Setup Time, HIGH or LOW 3.0 3.0 3.0 ts(L) J n or Kn to CPn 3.0 4.0 3.0 ns kk-kk th(H) Hold Time, HIGH or LOW 1.0 1.0 1.0 th(L) J n or Kn to CPn 1.0 1.0 1.0 tw (H) CP n Pulse Width 4.0 4.0 4.0 ns kk-kk tw (L) HIGH or LOW 5.0 5.0 5.0 tw (L) C Dn or SDn Pulse Width, 4.0 4.0 4.0 ns kk-kk LOW trec Recovery Time 2.0 2.0 2.0 ns kk-kk C Dn or SDn to CP

Ordering Information

The device number is used to form part of a simplified purchasing code where the package type and temperature range are de- fined as follows: DS009471-7 5 www.national.com PrintDate=1997/08/28 PrintTime=11:45:30 10182 ds009471 Rev. No. 1 cmservProof 5 Book Extract End DSXXX DSXXX DSXXX DSXXX DSXXX DSXXX DSXXX DSXXX Obsolete

THIS PAGE IS IGNORED IN THE DATABOOK PrintDate=1997/08/28 PrintTime=11:45:31 10182 ds009471 Rev. No. 1 cmservProof 6 Obsolete

Physical Dimensionsinches (millimeters) unless otherwise noted 20-Lead Ceramic Leadless Chip Carrier (L) 16-Lead Ceramic Dual-In-Line Package (D) 7 www.national.com PrintDate=1997/08/28 PrintTime=11:45:32 10182 ds009471 Rev. No. 1 cmservProof 7 Obsolete

Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) 16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC (S) 16-Lead (0.300" Wide) Molded Small Outline Package, EIAJ (SJ) PrintDate=1997/08/28 PrintTime=11:45:32 10182 ds009471 Rev. No. 1 cmservProof 8 www.national.com 8 Obsolete

Physical Dimensionsinches (millimeters) unless otherwise noted (Continued) 16-Lead (0.300" Wide) Molded Dual-In-Line Package (P) 16-Lead Ceramic Flatpak (F) 9 www.national.com 9 PrintDate=1997/08/28 PrintTime=11:45:33 10182 ds009471 Rev. No. 1 cmservProof 9 Obsolete

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE- VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI- CONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or sys- tems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose fail- ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop PrintDate=1997/08/28 PrintTime=11:45:33 10182 ds009471 Rev. No. 1 cmservProof 10 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Obsolete

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