74F109

74F109 PHILIPS | Alldatasheet

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/C0109 /C0110 /C0114 74F109 Positive J-K positive edge-triggered flip-flops Product specification IC15 Data Handbook

1990 Oct 23

Philips Semiconductors Product specification 74F109Postive J-K positive edge-triggered flip-flops 2October 23, 1990 853–0337 00783 FEATURE

• Industrial temperature range available (–40°C to +85°C)

DESCRIPTION

The 74F109 is a dual positive edge-triggered JK-type flip-flop featuring individual J, K, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock (CP) input. The J and K are edge-triggered inputs which control the state changes of the flip-flops as described in the function table. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. The J and K inputs must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. The JK design allows operation as a D flip-flop by tying J and K inputs together. Although the clock input is level sensitive, the positive transition of the clock pulse between the 0.8V and 2.0V levels should be equal to or less than the clock to output delay time for reliable operation. PIN CONFIGURATION 107 Q 0 VCC CP1 SD1 R D1 R D0 Q 0 CP0 SD0 98GND Q 1 SF00135 TYPE TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL) 74F109 125MHz 12.3mA

ORDERING INFORMATION

DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C INDUSTRIAL RANGE VCC = 5V ±10%, Tamb = –40°C to +85°C PKG DWG # 16-pin plastic DIP N74F109N I74F109N SOT38-4 16-pin plastic SO N74F109D I74F109D SOT109-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW J0, J1 J inputs 1.0/1.0 20µA/0.6mA K0, K1 K inputs 1.0/1.0 20µA/0.6mA CP0, CP1 Clock inputs (active rising edge) 1.0/1.0 20µA/0.6mA SD0, SD1 Set inputs (active Low) 1.0/3.0 20µA/1.8mA R D0, RD1 Reset inputs (active Low) 1.0/3.0 20µA/1.8mA Q0, Q1, Q0, Q1 Data outputs 50/33 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state. LOGIC SYMBOL J1J0 Q0 Q0 Q1 Q1 VCC = Pin 16 GND = Pin 8 K1K0 2 14 3 13 6 7 10 9 CP0 SD0 RD0 CP1 SD1 RD1 SF00136 IEC/IEEE SYMBOL SF00137 R S R S

Philips Semiconductors Product specification 74F109Postive J-K positive edge-triggered flip-flops October 23, 1990 3 LOGIC DIAGRAM VCC = Pin 16 GND = Pin 8 K QQ CP 4, 12 3, 13 6, 107, 9 2, 14 5, 11 1, 15 SD R D J SF00138 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE SD R D CP J K Q Q OPERATING MODE L H X X X H L Asynchronous set H L X X X L H Asynchronous reset L L X X X H H Undetermined* H H ↑ X X q q Hold H H ↑ h l q q Toggle H H ↑ h h H L Load ”1” (set) H H ↑ l l L H Load ”0” (reset) H H ↑ l h q q Hold ’no change” NOTES: H = High-voltage level h = High-voltage level one setup time prior to low-to-high clock transition L = Low-voltage level l = Low-voltage level one setup time prior to low-to-high clock transition q = Lower case indicate the state of the referenced output prior to the low-to-high clock transition X = Don’t care ↑ = Low-to-high clock transition = Not low-to-high clock transition * = Both outputs will be high if both SD and RD go low simultaneously ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in High output state –0.5 to VCC V IOUT Current applied to output in Low output state 40 mA T O perating free air temperature range Commercial range 0 to +70 °C Tamb Operating free-air temperature range Industrial range –40 to +85 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNITSYMBOL PARAMETER MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIN High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V IIK Input clamp current –18 mA IOH High-level output current –1 mA IOL Low-level output current 20 mA T O perating free air temperature range Commercial range 0 +70 °C Tamb Operating free-air temperature range Industrial range –40 +85 °C

Philips Semiconductors Product specification 74F109Postive J-K positive edge-triggered flip-flops October 23, 1990 4 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS 1 LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS 1 MIN TYP 2 MAX UNIT VO High level output voltage VCC = MIN, VIL = MAX, IO = MAX ±10%V CC 2.5 V VOH High-level output voltage VCC MIN, VIL MAX, VIH = MIN IOH = MAX ±5%V CC 2.7 3.4 V VO Low level output voltage VCC = MIN, VIL = MAX, IOL = MAX ±10%V CC 0.30 0.50 V VOL Low-level output voltage VCC MIN, VIL MAX, VIH = MIN ±5%V CC 0.30 0.50 V VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V II Input current at maximum input voltageVCC = MAX, VI = 7.0V 100 µA IIH High-level input current VCC = MAX, VI = 2.7V 20 µA I Low level input current J, K, CPn VCC = MAX, VI = 0.5V –0.6 mA IIL Low-level input current SDn, RDn VCC = MAX, VI = 0.5V –1.8 mA IOS Short-circuit output current3 VCC = MAX -60 –150 mA ICC Supply current4 (total) VCC = MAX 12.3 17 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS , the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn. AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25°C C L = 50pF R L = 500Ω VCC = +5.0V ± 10% Tamb = 0°C to +70°C C L = 50pF R L = 500Ω VCC = +5.0V ± 10% Tamb = –40°C to +85°C C L = 50pF R L = 500Ω UNIT MIN TYP MAX MIN MAX MIN MAX fMAX Maximum clock frequency Waveform 1 90 125 90 90 MHz tPLH tPHL Propagation delay CPn to Qn or Qn Waveform 1 3.8 4.4 5.3 6.2 7.0 8.0 3.8 4.4 8.0 9.2 3.8 4.4 9.0 9.2 ns tPLH tPHL Propagation delay S Dn, RD to Qn or Qn Waveform 2, 3 3.2 3.5 5.2 7.0 7.0 9.0 3.2 3.5 8.0 10.5 2.8 3.5 9.0 10.5 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION VCC = +5.0V Tamb = +25°C C L = 50pF R L = 500Ω VCC = +5.0V ± 10% Tamb = 0°C to +70°C C L = 50pF R L = 500Ω VCC = +5.0V ± 10% Tamb = –40°C to +85°C C L = 50pF RL = 500Ω UNIT MIN TYP MAX MIN MAX MIN MAX tsu (H) tsu(L) Setup time, high or low Dn to CPn Waveform 1 3.0 3.0 3.0 3.0 3.0 3.0 ns th (H) th (L) Hold time, high or low Dn to CPn Waveform 1 1.0 1.0 1.0 1.0 1.0 1.0 ns tw (H) tw (L) CP pulse width, high or low Waveform 1 4.0 5.0 4.0 5.0 4.0 5.0 ns tw (L) SDn or RDn pulse width, low Waveform 2 4.0 4.0 4.0 ns trec Recovery time S Dn or RDn to CP Waveform 3 2.0 2.0 2.0 ns

Philips Semiconductors Product specification 74F109Postive J-K positive edge-triggered flip-flops October 23, 1990 5 AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. VMVM CPn VM VM VM VM VM VM tsu(H) th(H) Jn, Kn Qn VM tw (H) 1/fmax tsu(L) th(L) VMVM tPLH Q n tw (L) tPHL tPHLtPLH SF00139 Waveform 1. Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Width,and Maximum Clock Frequency VMVM R Dn VM Qn VM VMVM tPLH Q n tw (L) tPHL tPHLtPLH SDn VMVM tw (L) SF00050 Waveform 2. Propagation Delay for Set and Reset to Output, Set and Reset Pulse Width SDn or RDn VM VM trec CPn SF00051 Waveform 3. Recovery Timer for Set or Reset to Clock

Philips Semiconductors Product specification 74F109Postive J-K positive edge-triggered flip-flops October 23, 1990 6 TEST CIRCUIT AND WAVEFORMS tw 90% VM 10% 90% VM 10% 90% VM 10% 90% VM 10% NEGATIVE PULSE POSITIVE PULSE tw AMP (V) tTHL (tf ) INPUT PULSE REQUIREMENTS rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns Input Pulse Definition VCC family 74F D.U.T.PULSE GENERATOR R LC LR T VIN VOUT Test Circuit for Totem-Pole Outputs DEFINITIONS: R L = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. C L = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. R T = Termination resistance should be equal to ZOUT of pulse generators. tTHL (tf ) tTLH (tr ) tTLH (tr ) AMP (V) amplitude 3.0V 1.5V VM SF00006

Philips Semiconductors Product specification 74F109Positive J-K positive edge-triggered flip-flops

1990 Oct 23 7

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

Philips Semiconductors Product specification 74F109Positive J-K positive edge-triggered flip-flops

1990 Oct 23 8

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Philips Semiconductors Product specification 74F109Positive J-K positive edge-triggered flip-flops

1990 Oct 23 9

Philips Semiconductors Product specification 74F109Positive J-K positive edge-triggered flip-flops yyyy mmm dd 10 Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors

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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381  Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Date of release: 10-98 Document order number: 9397-750-05069 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.