74F109

74F109 FAIRCHILD | Alldatasheet

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© 1999 Fairchild Semiconductor Corporation DS009471 www.fairchildsemi.com April 1988 Revised November 1999 74F109 Dual JK Positive Edge-Triggered Flip-Flop 74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The F109 consists of two high-speed, completely indepen- dent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop (refer to F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F109SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body 74F109SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE 11, 5.3mm Wide 74F109PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 ” Wide

www.fairchildsemi.com 2 74F109Truth Table H (h) = HIGH Voltage Level L (l) = LOW Voltage Level /c17 = LOW-to-HIGH Transition X = Immaterial Q 0 (Q0) = Before LOW-to-HIGH Transition of Clock Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition. Unit Loading/Fan Out Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Inputs Outputs SD C D CP J K QQ LHXXXHL HLXXXLH LLXXXHH HH /c17 II L H HH /c17 hI T o g g l e HH /c17 Ih Q Q HH /c17 hhHL HHLXXQQ Pin Names Description U.L. Input I IH/IIL HIGH/LOW Output I OH /IOL J1, J2, K1, K2 Data Inputs 1.0/1.0 20 µA/−0.6 mA CP 1, CP2 Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA C D1 , CD2 Direct Clear Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA SD1 , SD2 Direct Set Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA Q 1, Q2, Q1, Q2 Outputs 50/33.3 −1 mA/20 mA

3 www.fairchildsemi.com 74F109 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +175°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with Vcc = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Current Applied to Output in LOW State (Max) twice the rated I OL (mA) Free Air Ambient Temperature 0 °C to +70°C Supply Voltage +4.5V to +5.5V Symbol Parameter Min Typ Max Units VCC Conditions VIH Input HIGH Voltage 2.0 V Recognized as a HIGH Signal VIL Input LOW Voltage 0.8 V Recognized as a LOW Signal VCD Input Clamp Diode Voltage −1.2 V Min I IN = −18 mA VOH Output HIGH Voltage 10% V CC 2.5 VM i n IOH = −1 mA 5% VCC 2.7 I OH = −1 mA VOL Output LOW Voltage 10% V CC 0.5 V Min I OL = 20 mA IIH Input HIGH Current 5.0 µAM a x V IN = 2.7V IBVI Input HIGH Current Breakdown Test 7.0 µAM a x V IN = 7.0V ICEX Output HIGH Leakage Current 50 µAM a x V OUT = VCC VID Input Leakage Test 4.75 V 0.0 IID = 1.9 µA All Other Pins Grounded IOD Output Leakage 3.75 µA0 . 0 VIOD = 150 mV Circuit Current All Other Pins Grounded IIL Input LOW Current −0.6 mA Max V IN = 0.5V (Jn, Kn) −1.8 mA Max V IN = 0.5V (CDn , SDn ) IOS Output Short-Circuit Current −60 −150 mA Max V OUT = 0V ICC Power Supply Current 11.7 17.0 mA Max CP = 0V

www.fairchildsemi.com 4 74F109 AC Operating Requirements Symbol Parameter TA = +25°CT A = 0°C to +70°C Units VCC = +5.0V V CC = +5.0V C L = 50 pF C L = 50 pF Min Typ Max Min Max fMAX Maximum Clock Frequency 100 125 90 MHz ns tPHL C Dn or SDn to Q n or Qn Symbol Parameter TA = +25°CT A = 0°C to +70°C UnitsVCC = +5.0V V CC = +5.0V Min Max Min Max tS(H) Setup Time, HIGH or LOW 3.0 3.0 ns tS(L) J n or Kn to CPn 3.0 3.0 tH (H) Hold Time, HIGH or LOW 1.0 1.0 tH (L) J n or Kn to CPn 1.0 1.0 tW (H) CP n Pulse Width 4.0 4.0 ns tW (L) HIGH or LOW 5.0 5.0 tW (L) C Dn or SDn Pulse Width LOW 4.0 4.0 ns tREC Recovery Time 2.0 2.0 ns C Dn or SDn to CP

5 www.fairchildsemi.com 74F109 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A

www.fairchildsemi.com 6 74F109 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D

7 www.fairchildsemi.com 74F109 Dual JK Positive Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com